Design of a hardware security-embedded multimedia mobile processor

IEEE International Symposium on Communications and Information Technologies: ISCIT 2004

Volumn 1, Issue , 2004, Pages 362-367

  Fukase, Masa Aki ^a   Sato, Yoichi ^a   Sato, Tomoaki ^b  

^a HIROSAKI UNIVERSITY   (Japan)

^b SAPPORO GAKUIN UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; CRYPTOGRAPHY; DATA REDUCTION; IMAGE ANALYSIS; INTERNET; MOBILE TELECOMMUNICATION SYSTEMS; VERY LONG INSTRUCTION WORD ARCHITECTURE;

BUILT-IN FUNCTIONS; DIRECT COMMUNICATIONS; MOBILE PROCESSORS; PUBLIC KEY SCHEMES;

MULTIMEDIA SYSTEMS;

EID: 21844459258     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (31)

1. D. Saha and A. Mukherjee, "Pervasive Computing: A Paradigm for the 21st Century," Computer Magazine, Vol. 36, No. 3, pp. 25-31, Mar. 2003.
2. P. H. W. Leong and I. K. H. Leung, "A Microcoded Elliptic Curve Processor Using FPGA Technology," IEEE Trans, on VLSI Syst., Vol. 10, No. 5, pp. 550-559, Oct. 2002.
3. M. Fukase, K. Shioji, N. Imai, D. Murakami, and K. Mikuni, "An Experiment in the Design and Development of a Multimedia Processor for Mobile Computing," Technical Report of IEICE, Vol. 102, No. 400, pp. 13-18, Oct. 2002.
4. K. Mikuni, Y. Nakamura, and M. Fukase, "Architectural Aspects of Multimedia Mobile Processor Cores," Proc. of 2003 Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers, Japan, Aug. 2003.
5. Y. Nakamura, K. Mikuni, and M. Fukase, "Design Process of a Multimedia Mobile Processor Core," ibid.
6. K. Mikuni, Y. Nakamura, N. Imai, M. Fukase, and T. Sato, "Implementation of a Multimedia Mobile Processor," FIT2003, Sept. 2003.
7. M. Fukase, T. Sato, R. Egawa, and T. Nakamura, "Designing a Low Power and High Performance Multithreaded Java Microprocessor," 10 NASA Sympo. on VLSI Design, pp. 10.4.1-10.4.7, Mar. 2002.
8. M. Fukase, T. Sato, R. Egawa, and T. Nakamura, "Scaling up of Wave-Pipelines," Proc. of the Fourteenth International Conference on VLSI Design, pp. 439-445, Jan. 2001.
9. th SASIMI, pp. 351-356, Oct. 2001.
10. th NASA Symposium on VLSI Design, pp. 8.3.1-8.3.8, Mar. 2002.
11. R. Egawa, M. Fukase, T. Sato, and T. Nakamura, "Designing a 32-bit Wave-pipelined ALU," Proc. of ICCIT, pp. 490-494, Dec. 2002.
12. R. Egawa, M. Fukase, T. Sato, and T. Nakamura, "Could Wave Pipeline Overcome Commodity Pipelines?," Journal of Information, 2004 (In press).
13. M. Fukase, K. Progyana, and T. Nakamura, "Prototyping a Java-Embedded Multimedia Processor," IECON'01, pp. 2126-2130, Nov. 2001.
14. th NASA Symposium on VLSI Design, pp. 10.4.1-10.4.7, Mar. 2002.
15. P. Khondkar, M. Fukase, and T. Nakamura, "Designing a Floating-Point Unit for High-Level Language Integrated Media Processor," ICCIT, pp. 500-504, Dec. 2002.
16. P. Khondkar, M. Fukase, and T. Nakamura, "Design and Implementation Issues of Embedded Java Microprocessor," ICECE 2002, pp. 44-47, Dec. 2002.
17. P. Khondkar, M. Fukase, and T. Nakamura, "Enhancing Execution Bandwidth of Java-Embedded Processor," Information, Vol. 7, No. 2, pp. 215-225, Mar. 2004.
18. P. Khondkar, M. Fukase, C. Donizete Lima, and T. Nakamura, "An Architecture to Allow Intrinsic Concurrency on Java Processors for Embedded Systems," ibid, Vol. 7, No. 3, pp. 351-366, May 2004.
19. Z. Liu and M. Fukase, "An Application of a Random Number Generator," Workshop of IPSJ Tohoku Branch, July 1999.
20. M. Fukase T. Oyama, and Z. Liu, "Endeavor in the Field of Random Sampling-Designing and Prototyping a Processor Suited for its Acceleration," Technical Report of IEICE, Vol. 102, No. 272, pp. 7-12, Aug. 2002.
21. U. J. Kapasi, S. Rixner, W. J. Dally, B. Khailany, J. H. Ahn, P. Mattson, J. D. Owens, "Programmable Stream Processors," Computer Magazine, Vol. 36, No. 8, pp. 54-62, Aug. 2003.
22. D. Burger et al., "Scaling to the End of Silicon with EDGE Architectures," Computer Magazine, Vol. 37, No. 7, pp. 44-55, Jul. 2004.
23. L. D. Paulson, "Reversible Computing May Improve Mobile Performance," Computer Magazine, Vol. 37, No. 3, p. 21, Mar. 2004.
24. M. Fukase and T. Sato, "Power Conscious Endeavor in Processors to Speed Up Random Sampling", Proc. of SCI2003, Vol. V, pp. 111-116, Jul. 2003.
25. A. Fukase, Y. Sato, M. Fukase, T. Sato, and T. Araki, "Cryptographic System by a Random Addressing-Accelerated Multimedia Mobile Processor," FIT2003, Sept. 2003.
26. M. Fukase, A. Fukase, Y. Sato, and T. Sato, "Cryptographic System by a Random Addressing-Accelerated Multimedia Mobile Processor," Proc. of SCI2004, Vol. II, pp. 174-179, Jul. 2004.
27. M. Fukase, A. Fukase, Y. Sato, and T. Sato, "Exploiting a Hardware Security-Embedded Multimedia Mobile Processor System and its Application," ITC-CSCC, pp. 7C3L-3-1-7C3L-3-4, Jul. 2004.
28. S. Wang and S. K. Gupta, "DS-LFSR: A BIST TPG for Low Switching Activity," IEEE Trans, on CAD of IC and Syst., Vol. 21, No. 7, pp. 842-851, July 2002.
29. D. Kagaris, "Linear Dependencies in Extended LFSMs," IEEE Trans, on CAD of IC and Syst., Vol. 21, No. 7, pp. 852-859, Jul. 2002.
30. http://www.shadowpenguin.org/sc_documents/spsdocument12.html
31. M. Katoh, M Fukase, and T. Nakamura, "A Decoding Algorthm of BHC Code," The Science Reports of the Hirosaki University, Vol. 44, No. 1, pp. 119-123, Aug. 1997.