Simulation of gate lag and current collapse in GaN Heterojunction Field Effect Transistors

Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC

Volumn , Issue , 2004, Pages 287-290

  Braga, N ^a   Mickevicius, R ^a   Shur, M ^b   Gaska, R ^c   Khan, M Asif ^d   Simin, G ^d  

^a Integrated Systems Inc   (United States)

^b RENSSELAER POLYTECHNIC INSTITUTE   (United States)

^c SENSOR ELECTRONIC TECHNOLOGY INC   (United States)

^d The Department of Mechanical Engineering   (United States)

Author keywords

Current collapse; GaN HFET; Simulation

Indexed keywords

CIRCUIT SIMULATIONS; CURRENT COLLAPSE; GALLIUM NITRIDE HETEROJUNCTION FIELD EFFECT TRANSISTORS (HFET); GATE LAG;

COMPUTER SIMULATION; CURRENT DENSITY; ELECTRON TRANSITIONS; ELECTRON TRAPS; FIELD EFFECT TRANSISTORS; GATES (TRANSISTOR); HETEROJUNCTIONS; MESFET DEVICES; MOSFET DEVICES;

GALLIUM NITRIDE;

EID: 21644476044     PISSN: 15508781     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CSICS.2004.1392569     Document Type: Conference Paper

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