Analytical model for the threshold voltage of Dual Material Gate (DMG) partially depleted SOI MOSFET and evidence for reduced short-channel effects

International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT

Volumn 2, Issue , 2004, Pages 1204-1207

  Kumar, M Jagadesh ^a   Reddy, G Venkateshwar ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE CARRIERS; COMPUTER SIMULATION; CONCENTRATION (PROCESS); DOPING (ADDITIVES); ELECTRIC FIELD EFFECTS; GATES (TRANSISTOR); SILICON ON INSULATOR TECHNOLOGY; SURFACES; THIN FILMS; THRESHOLD VOLTAGE;

DOPING CONCENTRATIONS; DUAL MATERIAL GATE (DMG); FILM THICKNESS; SHORT-CHANNEL EFFECTS;

MOSFET DEVICES;

EID: 21644449766     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. A. Chaudhry and M. J. Kumar, IEEE Trans. on Device and Materials Reliability, 4, p. 99 (2004).
2. M. J. Kumar and V. Verma, IEEE Trans. on Reliability, 51, p.367 (2002).
3. M. J. Kumar and A. Chaudhry, IEEE Tran. on Electron Devices, 15, p.569 (2004).
4. W. Long, H. Ou, J.-M. Kuo, and K. K. Chin, IEEE Trans. on Electron Devices, 46, p. 865 (1999).
5. K. K. Young, IEEE Trans. Electron Devices, 36. p.399 (1989).
6. MEDICI, Technology Modelling Associates Inc, Palo Alto, CA, 1997.