Elimination of bipolar induced drain breakdown and single transistor latch in submicron PD SOI MOSFET

IEEE Transactions on Reliability

Volumn 51, Issue 3, 2002, Pages 367-370

  Kumar, M Jagadesh ^a,b   Verma, Vikram ^c  

^a IEEE   (India)

^b INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

^c TEXAS INSTRUMENTS   (India)

Author keywords

CMOS reliability; Drain breakdown; Floating body effect; Single transistor latch; SOI MOSFET

Indexed keywords

BIPOLAR INDUCED DRAIN BREAKDOWN; CMOS RELIABILITY; FLOATING BODY EFFECT; PARTIALLY DEPLETED SILICON ON INSULATOR MOSFET; SINGLE TRANSISTOR LATCH;

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC BREAKDOWN; MOSFET DEVICES; PERFORMANCE; SEMICONDUCTING SILICON COMPOUNDS; SILICON ON INSULATOR TECHNOLOGY; VLSI CIRCUITS;

RELIABILITY;

EID: 0036733286     PISSN: 00189529     EISSN: None     Source Type: Journal    
DOI: 10.1109/TR.2002.801851     Document Type: Article

References (9)

1. Scalable PD/SOI CMOS with floating bodies
2. Parasitic bipolar gain reduction and the optimization of 0.25 μm partially depleted SOI MOSFET's
3. LDD design trade-offs for single transistor latch-up and hot-carrier degradation control in accumulation mode FD SOI MOSFET's
4. Suppression of floating body effect in PD SOI MOSFET's with Si-Ge source structure and its mechanism
5. Suppressing the parasitic bipolar action in fully depleted MOSFETs/SIMOX by using backside bias-temperature treatment
6. + dual source structure for eliminating bipolar induced breakdown in submicron SOI MOSFETs
7. A 0.1 μm delta-doped MOSFET fabricated with post-low-energy implanting selective epitaxy