Complementary self-biased logics based on single-electron transistor (SET)/CMOS hybrid process

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 44, Issue 4 B, 2005, Pages 2618-2622

  Song, Ki Whan ^a   Lee, Yong Kyu ^a   Sim, Jae Sung ^a   Kim, Kyung Rok ^a   Lee, Jong Duk ^a   Park, Byung Gook ^a   You, Young Sub ^b   Park, Joo On ^b   Jin, You Seung ^b   Kim, Young Wug ^b  

^a Seoul National University   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

CMOS; Coulomb; Multi valued logic; SET; Single electron transistor; Tunnelling

Indexed keywords

CMOS INTEGRATED CIRCUITS; COULOMB BLOCKADE; ELECTRON TUNNELING; HIGH TEMPERATURE EFFECTS; OSCILLATIONS; PHASE CONTROL;

CMOS; COULOMB; MULTI-VALUED LOGIC; SET; SINGLE ELECTRON TRANSISTORS;

TRANSISTORS;

EID: 21244493578     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/JJAP.44.2618     Document Type: Conference Paper

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