Low-power FFT/IFFT VLSI macro cell for scalable broadband VDSL modem

Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003

Volumn , Issue , 2003, Pages 161-166

  Saponara, S ^a   Serafini, L ^a   Fanucci, L ^b  

^a UNIVERSITY OF PISA   (Italy)

^b CNR   (Italy)

Author keywords

Circuit optimization; Circuit synthesis; Clocks; CMOS technology; DSL; Energy consumption; Fast Fourier transforms; Modems; Very large scale integration; Voltage

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CLOCKS; CMOS INTEGRATED CIRCUITS; COST EFFECTIVENESS; DSL; ELECTRIC POTENTIAL; ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTRIC POWER UTILIZATION; ENERGY UTILIZATION; MICROPROCESSOR CHIPS; MODEMS; PROGRAMMABLE LOGIC CONTROLLERS; REAL TIME SYSTEMS; SIGNAL RECEIVERS; SYNTHESIS (CHEMICAL); TELECOMMUNICATION LINES; TELEPHONE LINES; VLSI CIRCUITS; VOLTAGE SCALING;

CASCADE ARCHITECTURE; CIRCUIT OPTIMIZATION; CIRCUIT SYNTHESIS; CMOS TECHNOLOGY; DIGITAL SUBSCRIBER LINE SYSTEMS; LOW POWER DESIGN TECHNIQUE; SUPPLY-VOLTAGE SCALING; SWITCHING ACTIVITY REDUCTION;

FAST FOURIER TRANSFORMS;

EID: 21244483681     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWSOC.2003.1213027     Document Type: Conference Paper

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