COBRA: A 100-MOPS single-chip programmable and expandable FFT

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 7, Issue 2, 1999, Pages 174-182

  Chen, Tom ^a   Sunada, Glen ^a   Jin, Jian ^b  

^a Engineering Research Center and Hydraulics Laboratory   (United States)

^b Trident Microsystems Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; DESIGN FOR TESTABILITY; DIGITAL ARITHMETIC; FAST FOURIER TRANSFORMS; INTEGRATED CIRCUIT TESTING;

BIT PARALLEL ARITHMETIC; BIT SERIAL ARITHMETIC;

VLSI CIRCUITS;

EID: 0032675914     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.766744     Document Type: Article

References (15)

1. J. W. Cooley and J. W. Tukey, "An algorithm for the machine calculation of complex Fourier series," Math. Comput., vol. 20, pp. 429-430, July 1966.
2. W. M. Gentleman and G. Sande, "Fast Fourier transforms - For fun and profit," in ASIPS Fall Joint Computer Conf., vol. 29, pp. 563-578, 1966.
3. M. C. Pease, "An adaptation of the fast Fourier transform for parallel processing," J. Assoc. Comput. Machin., vol. 15, no. 2, pp. 252-264, Apr. 1968.
4. B. Gold and T. Bially, "Parallelism in Fourier transform hardware," IEEE. Trans. Audio Electroacous., vol. AU-21, pp. 5-16, Jan. 1973.
5. J. Brien, J. Mather, and B. Holland, "A 200-MIP single chip 1K FFT processor," in 36th IEEE Int. Solid-State Circuits Conf., 1988, pp. 166-167.
6. S. Shen, S. Magar, and R. Aguilar, "A high performance CMOS chipset for FFT processors," in IEEE. Int. Conf. Computer Design, 1988, pp. 578-581.
7. P. Raberts and N. Magatra, "FFT-based VLSI digital array signal processor," in IEEE. Int. Conf. Syst. Eng., 1989, pp. 285-288.
8. K. Yamashita, "A wafer-scale FFT processor featuring a repeatable building block," Int. Conf. Wafer-Scale Integration, 1989, pp. 299-307.
9. J. You and S. S. Wong, "A high performance single chip FFT array processor for wafer scale integration," Int. Conf. Wafer-Scale Integration, 1990, pp. 60-67.
10. D. L. Allen and A. H. Anderson, "MUSE: A wafer-scale systolic DSP," in Int. Conf. Wafer-Scale Integration, 1990, pp. 27-35.
11. J. E. Whelchel, J. P. O'Malley, and W. J. Rinard, "The systolic phase rotation FFT - A new algorithm and parallel processor architecture," in IEEE ICASSP, 1990, pp. 1021-1024.
12. K. M. Guttag, R. J. Gove, and J. R. Van Aken "A single-chip multiprocessor for multimedia: The MVP," in IEEE Comput. Graphics Applicat. Conf., Nov. 1992, pp. 75-86.
13. T. Chen and L. Zhu, "An expandable column FFT architecture using circuit switching networks," J. VLSI Signal Processing, vol. 5, no. 6, pp. 243-257, 1993.
14. R. J. Gove, "The MVP: A highly-integrated video compression chip," in Data Compression Conf., 1994, pp. 215-224.
15. P. Denyer and D. Renshaw, VLSI Signal Processing. Reading, MA: Addison-Wesley, 1985.