A new memory-based FFT processor for VDSL transceivers

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 4, Issue , 2001, Pages 670-673

  Wang, Chin Liang ^a   Chang, Ching Hsien ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGY; COMPLEX MULTIPLIERS; DISCRETE MULTI-TONE; FAST ALGORITHMS; FAST COMPUTATION; FFT PROCESSORS; HIGH-THROUGHPUT; VLSI ARCHITECTURES;

CLOCKS; CMOS INTEGRATED CIRCUITS; DISCRETE FOURIER TRANSFORMS; RANDOM ACCESS STORAGE; TRANSCEIVERS;

DESIGN FOR TESTABILITY;

EID: 0012656524     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.922326     Document Type: Conference Paper

References (11)

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3. VDSL Alliance SDMT VDSL Draft Standard Proposal, ETSI STC/TM6, April 1998.
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