Evaluation of platform architecture performance using abstract instruction-level workload models

2004 International Symposium on System-on-Chip Proceedings

Volumn , Issue , 2004, Pages 43-48

  Kreku, Jari ^a   Kauppi, Tarja ^a   Soininen, Juha Pekka ^a  

^a VTT TECHNICAL RESEARCH CENTRE OF FINLAND   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER APPLICATIONS; COMPUTER SIMULATION; DATA REDUCTION; DECISION MAKING; EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; PARAMETER ESTIMATION; SCHEDULING; SOFTWARE PROTOTYPING;

DOMAIN-SPECIFIC PLATFORM ARCHITECTURES; INSTRUCTION-LEVEL WORKLOAD MODELS; MULTI-PROCESSOR PLATFORMS; PLATFORM ARCHITECTURE PERFORMANCE;

COMPUTER ARCHITECTURE;

EID: 21244461544     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)

1. L. Benini, G. De Micheli, Networks on chip: a new SoCparadigm, Computer, Vol. 35, No. 1, Pp. 70-78.
2. International Technology Roadmap for Semiconductors - 2003 Edition, Executive Summary, 75 p., available at http://public.itrs.net.
3. W. Wolf, Computers and Components - Principles of Embedded Computing System Design. Morgan Kaufmann Publishers, 2001, 662 p.
4. J. Hennessy, D. Patterson, Computer Architecture A Quantitative Approach, 3rd edition, Morgan Kaufmann Publishers, 2003, 883 p.
5. R. Jain, The Art of Computer Systems Performance Analysis: Techniques for Experimental Design, Measurement, Simulation and Modeling, John Wiley & Sons, Inc, 1991, 685p.
6. D. Petriu et al, Architecture-based Performance Analysis Applied to a Telecommunication System, IEEE Transactions on Software Engineering, Vol. 26, No. 11, pp. 1049-1065.
7. J. Staunstrup, W. Wolf, Hardware/software codesign: principles and practice, Kluwer Academic Publishers, Boston, MA, USA, 395 p.
8. J. Rowson, Hardware/Software Co-Simulation, 1994. Proceedigns of 31st Design Automation Conference. Pp. 439-440.
9. T. Austin et al, Simplescalar: an Infrastructure for Computer System Modeling, IEEE Computer, Vol. 35, No. 2, 2002, pp. 59-67.
10. rd Design Automation Conference, Las Vegas, NV, USA, 3-7 June, 1996, pp. 690-695.
11. th Design Automation Conference, Anaheim, CA, USA, 9-13 June 1997, pp. 178-183.
12. A. Wieferink et al, System Level Processor/Communication Co-exploration Methodology for Multi-processor System-on-Chip Platforms, Proceedings of Design Automation and Test in Europe, DATE 2004, Paris, France, 16-20 February 2004, pp. 1256-1261.
13. th International Conference on VLSI Design, Calcutta, India, 3-7 January 2000, pp. 530-537.
14. M. Lazarescu et al. 2000 Compilation-based Software Performance Estimation for System Level Design. Proceedings of High Level Design Validation and Test Workshop. Berkeley, CA,USA, 8-10 November, 2000. Pp. 167-172
15. C. Krishna (ed). 1996. Performance Modeling for Computer Architects. IEEE CS Press. 391 p.