Compilation-based software performance estimation for system level design

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Volumn 2000-January, Issue , 2000, Pages 167-172

  Lezerescu M T ^a   Bammi, J R ^a   Harcourt, E ^a   Lavagno, L ^b   Lajolo, M ^c  

^a CADENCE DESIGN SYSTEMS   (United States)

^b UNIVERSITY OF UDINE   (Italy)

^c NEC LABORATORIES AMERICA   (United States)

Author keywords

Clocks; Computer architecture; Costs; Delay estimation; Embedded system; Hardware; Real time systems; Software performance; System level design; Timing

Indexed keywords

CLOCKS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SOFTWARE; COSTS; DESIGN; EMBEDDED SYSTEMS; INTERACTIVE COMPUTER SYSTEMS; REAL TIME SYSTEMS; VERIFICATION;

BEHAVIORAL SIMULATION; DELAY ESTIMATION; INSTRUCTION SET SIMULATORS; SOFTWARE PERFORMANCE; SOFTWARE PERFORMANCE ESTIMATIONS; SOFTWARE SIMULATION; SYSTEM LEVEL DESIGN; TIMING;

C (PROGRAMMING LANGUAGE);

EID: 84949676876     PISSN: 15526674     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HLDVT.2000.889579     Document Type: Conference Paper

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