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Volumn 17, Issue 1, 2005, Pages 24-32

Sub process challenges in ultra fine pitch stencil printing of type-6 and type-7 Pb-free solder pastes for flip chip assembly applications

Author keywords

Integrated circuit technology; Printed circuits; Solder

Indexed keywords

COST EFFECTIVENESS; ELECTRONIC EQUIPMENT; FLIP CHIP DEVICES; INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; PRINTED CIRCUITS; RHEOLOGY; TRANSISTORS;

EID: 18844366438     PISSN: 09540911     EISSN: None     Source Type: Journal    
DOI: 10.1108/09540910510579212     Document Type: Conference Paper
Times cited : (26)

References (17)
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  • 3
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    • Critical factors affecting paste flow during the stencil printing of solder paste
    • Durairaj, R.K., Nguty, T.A. and Ekere, N.N. (2001), "Critical factors affecting paste flow during the stencil printing of solder paste", Soldering & Surface Mount Technology, Vol. 13 No. 2, pp. 30-4.
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    • Durairaj, R.K.1    Nguty, T.A.2    Ekere, N.N.3
  • 4
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    • Correlation of solder paste rheology with computational simulations of the stencil printing process
    • Durairaj, R.K., Jackson, G.J., Ekere, N.N., Glinski, G. and Bailey, C. (2002), "Correlation of solder paste rheology with computational simulations of the stencil printing process", Soldering & Surface Mount Technology, Vol. 14 No. 1, pp. 11-17.
    • (2002) Soldering & Surface Mount Technology , vol.14 , Issue.1 , pp. 11-17
    • Durairaj, R.K.1    Jackson, G.J.2    Ekere, N.N.3    Glinski, G.4    Bailey, C.5
  • 5
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    • Proceedings of the 27th IEEE/SEMI, International Electronics Manufacturing Technology Symposium, San Jose, CA
    • Huang, B. and Lee, N-C. (2002), "Solder bumping via paste reflow for area array packages", Proceedings of the 27th IEEE/SEMI, International Electronics Manufacturing Technology Symposium, San Jose, CA, pp. 1-17.
    • (2002) Solder Bumping via Paste Reflow for Area Array Packages , pp. 1-17
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    • Suhir, E.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.