Ramp Input Response of RC Tree Networks

Analog Integrated Circuits and Signal Processing

Volumn 14, Issue 1-2, 1997, Pages 53-58

  Friedman, Eby G ^{a,b,c,d,e,f,g}   Mulligan Jr , J H ^{b,h,i,j,k,l,m,n}  

^a University of Rochester   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c LAFAYETTE COLLEGE   (United States)

^d PHILIPS RESEARCH LABORATORIES   (Germany)

^e UNIVERSITY OF ROCHESTER   (United States)

^f High Perf VLSI/IC Des Anal Lab   (United States)

^g IEEE   (United States)

^h Cooper Union School of Engineering ^*  (United States)

ⁱ STEVENS INSTITUTE OF TECHNOLOGY   (United States)

^j Och Spine at New York Presbyterian Hospitals   (United States)

^k LUCENT TECHNOLOGIES   (United States)

^l POLYTECHNIC UNIVERSITY   (United States)

^m NATIONAL ACADEMY OF ENGINEERING   (United States)

ⁿ University of California at Irvine   (United States)

more..

Author keywords

Interconnect impedance; Ramp input response; RC trees

Indexed keywords

DELAY CIRCUITS; DIGITAL CIRCUITS; ELECTRIC IMPEDANCE; ESTIMATION; TRANSFER FUNCTIONS; VLSI CIRCUITS;

TREE NETWORKS;

INTEGRATED CIRCUITS;

EID: 0031238343     PISSN: 09251030     EISSN: None     Source Type: Journal    
DOI: 10.1007/978-1-4615-6101-9_5     Document Type: Article

References (11)

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