Efficient implementation of a complex ±1 multiplier

GLSVLSI 2002 - Proceedings of the 12th ACM Great Lakes Symposium on VLSI

Volumn , Issue , 2002, Pages 83-88

  Andreev, Boris D ^a   Friedman, Eby G ^a   Titlebaum, Edward L ^a  

^a University of Rochester   (United States)

Author keywords

CDMA; PN code; Redundant arithmetic; Scrambler; VLSI

Indexed keywords

INTEGRATED CIRCUIT TESTING; LOGIC CIRCUITS; VLSI CIRCUITS;

CDMA COMMUNICATION SYSTEMS; COMPLEX MULTIPLIERS; CRITICAL PATH DELAYS; EFFICIENT IMPLEMENTATION; PN CODE; REDUNDANT ARITHMETIC; SCRAMBLER; VLSI;

CODE DIVISION MULTIPLE ACCESS;

EID: 0012983455     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/505306.505325     Document Type: Conference Paper

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