Model-based design improvements for the 100 nm lithography generation

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 4691, Issue 1, 2002, Pages 215-226

  Lucas, Kevin ^a   Postnikov, Sergei ^a   Patterson, Kyle ^a   Yuan, Chi Min ^a   Thomas, Carla ^a   Thompson, Matt ^a   Carter, Rusty ^a   Litt, Lloyd ^a   Montgomery, Patrick ^a,b   Wimmer, Karl ^a  

^a MOTOROLA INC   (United States)

^b MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SOFTWARE; DEFORMATION; GATES (TRANSISTOR); LOGIC DEVICES; MASKS; PHASE SHIFT;

COMPLEX PATTERNING TECHNIQUES;

PHOTOLITHOGRAPHY;

EID: 18644374986     PISSN: 0277786X     EISSN: None     Source Type: Journal    
DOI: 10.1117/12.474563     Document Type: Article

References (6)

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3. V. Van Driessche, K. Lucas, F. Van Roey, G. Grozev, P. Tzviatkov. 100 nm Generation Contact Patterning by Low Temperature 193 nm Resist Reflow Process. Proc. of SPIE Vol. 4690, 2002, to be published.
4. S. Parihar, et. al. A High Density 0.10μm CMOS Technology Using Low K Dielectric and Copper Interconnect. Proc. of IEDM 2001.
5. T.L. Perkinson, L.C. Litt, J.G. Maltabes, S. Murphy, R.R. Hershey. Who needs I-line? Future Fab Issue 3, Vol. 1. 1998.
6. M. Reiger, J. Mayhew, Z. Tang, J. Shiely. Verifying RET mask layouts. Proc. of SPIE Vol. 4692B, 2002, to be published.