Ternary static latch circuit

International Journal of Electronics

Volumn 88, Issue 1, 2001, Pages 53-58

  Current, K W ^a  

^a University of California Davis   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 1842789985     PISSN: 00207217     EISSN: None     Source Type: Journal    
DOI: 10.1080/00207210150198284     Document Type: Article

References (13)

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11. THOIDIS, I., SOUDRIS, D., KARAFYLLIDIS, I., THANAILAKIS, A., and STOURAITIS, T., 1998 a, Multiple-valued logic voltage-mode storage circuits based upon true-signal-phase clocked logic. Proceedings of the 8th Great Lakes Symposium on VLSI, pp. 83-88.
12. THOIDIS, I., SOUDRIS, D., KARAFYLLIDIS, I., THANAILAKIS, A., and STOURAITIS, T., 1998 b, Design methodology of multiple-valued logic voltage-mode storage circuits. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, pps. 125-128.
13. ZHUANG, N., and Wu, H., 1990, Novel ternary JKL flip-flop. Electronics Letters, 26, 1145-1146.