Ternary latches for tddnl pipelined systems

International Journal of Electronics

Volumn 80, Issue 4, 1996, Pages 547-560

  Herrfeld, Andreas ^a   Hentschke, Siegbert ^a  

^a UNIVERSITY OF KASSEL   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; LOGIC CIRCUITS; PIPELINE PROCESSING SYSTEMS;

TERNARY DYNAMIC DIFFERENTIAL NORA LOGIC (TDDNL); TERNARY LATCHES;

FLIP FLOP CIRCUITS;

EID: 0030126932     PISSN: 00207217     EISSN: 13623060     Source Type: Journal    
DOI: 10.1080/002072196137183     Document Type: Article

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