Voltage-mode CMOS quaternary latch circuit

Electronics Letters

Volumn 30, Issue 23, 1994, Pages 1928-1929

  Current, K W ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

CMOS integrated circuits; Many valued logics

Indexed keywords

COMPARATOR CIRCUITS; ELECTRIC NETWORK ANALYSIS; FLIP FLOP CIRCUITS; LOGIC GATES; MANY VALUED LOGICS; MATHEMATICAL MODELS; SIGNAL PROCESSING;

CMOS QUATERNARY LATCH CIRCUIT; VOLTAGE MODE;

CMOS INTEGRATED CIRCUITS;

EID: 0028548681     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19941299     Document Type: Article

References (3)

1. DRUZETA, A., and SEDRA, A.S.: ‘Multithreshold circuits in the design of multi-state storage elements’. Proc. 1973 Int. Symp. Multiple Valued Logic, 1973, pp. 49–58
2. DRUZETA, A., VRANESIC, Z., and SEDRA, A.S.: ‘Application of multithreshold elements in the realization of many-valued logic networks’, IEEE Trans., C-23, pp. 1194–1198
3. HURST, S.L.: ‘Multiple valued logic its status and future’, IEEE Trans.,C-33, pp. 1160–1179