Design methodology of Multiple-Valued Logic voltage-mode storage circuits

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 1998, Pages 125-128

  Thoidis, I ^a   Soudris, D ^a   Karafyllidis, I ^a   Thanailakis, A ^a   Stouraitis, T ^a  

^a DEMOCRITUS UNIVERSITY OF THRACE   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE EQUIPMENT; ELECTRIC NETWORK ANALYSIS; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; ITERATIVE METHODS; LOGIC GATES; MOSFET DEVICES; TIMING CIRCUITS; VLSI CIRCUITS;

MULTIPLE-VALUED LOGIC VOLTAGE MODE STORAGE CIRCUITS; TRUE SINGLE-PHASE CLOCKED LOGIC-BASED OUTPUT UNITS; UNI-SIGNAL CONTROLLED PASS GATES;

LOGIC CIRCUITS;

EID: 0031642712     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)