Comments on "the digit parallel method for fast RNS to weighted number system conversion for specific moduli (2k - 1, 2k, 2k + 1)"

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 47, Issue 9, 2000, Pages 972-974

  Ananda Mohan, P V ^a  

^a ITI Ltd   (India)

Author keywords

Residue arithmetic; Residue numbers; Reverse converters

Indexed keywords

DIGITAL ARITHMETIC; NUMBER THEORY; THEOREM PROVING;

RESIDUE NUMBER SYSTEMS (RNS); WEIGHTED NUMBER SYSTEMS;

PARALLEL PROCESSING SYSTEMS;

EID: 0034270225     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.868470     Document Type: Article

References (4)

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2. S. Andraros and H. Ahmed A new efficient memory-less residue to binary converter," IEEE Trans. Circuits Syst., vol. CAS-35, pp. 1441-1445, Sept. 1988.
3. S. J. Piestrak A high-speed realization of a residue to binary system converter," IEEE Trans. Circuits Syst. II, vol. 42, pp. 661-663, 1995.
4. R. P. Brent and H. T. Kung A regular layout for parallel adders," IEEE Trans. Comput., vol. C-31, pp. 260-264, 1982.