Hardware Object Model and Its Application to the Image Processing

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E87-A, Issue 3, 2004, Pages 547-558

  Kudo, Kenji ^a   Myokan, Yoshihiro ^a   Than, Winh Chan ^a   Akimoto, Shinji ^a   Kanamaru, Takashi ^a   Sekine, Masatoshi ^a  

^a TOKYO UNIVERSITY OF AGRICULTURE AND TECHNOLOGY   (Japan)

Author keywords

Hardware object model; Reconfigurable computing system; Template matching; Wavelet transformation

Indexed keywords

C (PROGRAMMING LANGUAGE); COMPUTATION THEORY; COMPUTER HARDWARE; FIELD PROGRAMMABLE GATE ARRAYS; MATHEMATICAL MODELS; PATTERN MATCHING; PROGRAM COMPILERS; RAPID PROTOTYPING; SIGNAL PROCESSING; USER INTERFACES; WAVELET TRANSFORMS;

HARDWARE OBJECT MODELS; RECONFIGURABLE COMPUTING SYSTEMS; TEMPLATE MATCHING;

IMAGE PROCESSING;

EID: 1842586158     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (19)

1. R. Tessier and W. Burleson, "Reconfigurable computing for digital signal processing: A survey," J. VLSI Signal Process., vol.28, pp.7-27, 2001.
2. Y. Sueyoshi and M. Iida, "Configurable and reconfigurable computing for digital signal processing," IEICE Trans. Fundamentals, vol.E85-A, no.3, pp.591-599, March 2002.
3. H. Amano, Y. Shibata, and M. Uno, "Reconfigurable systems; New activities in Asia," Proc. FPL2000, pp.585-594, 2000.
4. E. Caspi, M. Chu, R. Huang, J. Yen, Y. Markovskiy, A. DeHon, and J. Wawrzynek, "Stream computations organized for reconfigurable execution (SCORE): Introduction and tutorial," http://www.cs.berkeley.edu/projects/ brass/documents/score_tutorial.html.
5. J.R. Hauser and J. Wawrzynek, "Garp: A MIPS processor with a reconfigurable coprocessor," Proc. IEEE Workshop on FPGAs for Custom Computing Machines, pp.24-33, 1997.
6. D.A. Buell, J.M. Arnold, and W.J. Kleinfelder, Splash 2: FPGAs in a Custom Computing Machine, Wiley-IEEE Press, 1996.
7. J.E. Vuillemin, P. Bertin, D. Roncin, M. Shand, H.H. Touati, and P. Boucard, "Programmable active memories: Reconfigurable systems come of age," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.4, no.1, pp.56-69, 1996.
8. P. Bellows and B. Hutchings, "JHDL - An HDL for reconfigurable systems," Proc. IEEE Workshop on FPGAs for Custom Computing Machines, pp.175-184, 1998.
9. M. Chu, N. Weaver, K. Sulimma, A. DeHon, and J. Wawrzynek, "Object oriented circuit-generators in Java," Proc. IEEE Workshop on FPGAs for Custom Computing Machines, pp.158-166, 1998.
10. D. Davis, M. Barr, T. Bennett, S. Edwards, J. Harris, I. Miller, and C. Schanck, "A Java development and runtime environment for reconfigurable computing," Proc. 5th Reconfigurable Architectures Workshop, pp.43-48, 1998.
11. M. Sekine,T. Kanamaru, K. Kudo, H. Imanaka, Y. Shiga, H. Ito, and Y. Myokan, "Hardware objects of the circuits for robotics," Proc. 2003 IEEE International Symposium on Computational Intelligence in Robotics and Automation, pp. 1421-1426, 2003.
12. JTAG is an abbreviation for joint test action group. The standard test access port and boundary scan architecture was standardized as IEEE 1149.1 in 1990.
13. Opencores web site, http://www.opencores.org/
14. S. Mallat, A wavelet tour of signal processing, Academic Press, 1999.
15. T. Yahagi, H. Ito, K. Noguchi, and H. Fujiwara, VLSI and Digital Signal Processing, pp.202-205, Corona Pub., 1997.
16. M. Sekine, T. Kanamaru, and H. Ito, "Multi-level matching for detecting faces," IEICE Trans. Fundamentals (Japanese Edition), vol.J86-A, no.9, pp.969-973, Sept. 2003.
17. T. Kohonen, Self-organizing maps, Springer-Verlag, 2000.
18. SpecC web site, http://www.specc.org/
19. Systeme web site, http://www.systemc.org/