Applying equivalent scaling to USJ implantation

Semiconductor International

Volumn 28, Issue 1, 2005, Pages 52-55

  Borland, John O ^a   Tanjyo, Masayasu ^b   Nagai, Nobuo ^b   Aoyama, Takayuki ^c   Jacobson, Dale ^d  

^a JOB Technologies   (United States)

^b NISSIN ION EQUIPMENT CO LTD   (Japan)

^c FUJITSU LABORATORIES LTD   (Japan)

^d Ceradyne Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

END-OF-RANGE (EOR); MULTIPURPOSE IMPLANTER (MPI); PRE-AMORPHIZING IMPLANT (PAI); SCALING; ULTRASHALLOW JUNCTION (USJ);

AMORPHIZATION; ANNEALING; BORON; CMOS INTEGRATED CIRCUITS; CONTAMINATION; DOPING (ADDITIVES); GATES (TRANSISTOR); ION IMPLANTATION; LEAKAGE CURRENTS; LOGIC DEVICES; TRANSMISSION ELECTRON MICROSCOPY;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 18144393774     PISSN: 01633767     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Review

References (18)

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