High-tilt implant and diffusion-less activation for lateral graded S/D engineering

Solid State Technology

Volumn 46, Issue 6, 2003, Pages 52-54+56+58

  Borland, John O ^a   Moroz, Victor ^b   Wang, Howard ^c   Maszara, Witek ^d   Iwai, Hiroshi ^e  

^a Varian Semiconductor Equip Assoc   (United States)

^b SYNOPSYS INC   (United States)

^c TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

^d ADVANCED MICRO DEVICES   (United States)

^e TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRONICS INDUSTRY; EMBEDDED SYSTEMS; GATES (TRANSISTOR); LOGIC DEVICES; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR STORAGE; SILICON ON INSULATOR TECHNOLOGY; SILICON WAFERS;

MULTIGATE DEVICES; SYSTEM-ON-A-CHIP;

INTEGRATED CIRCUIT LAYOUT;

EID: 0038148212     PISSN: 0038111X     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Article

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