Affordable and effective screening of delay defects in ASICs using the Inline resistance fault model

Proceedings - International Test Conference

Volumn , Issue , 2004, Pages 1285-1294

  Benware, Brady ^a   Lu, Cam ^a   Van Slyke, John ^a   Krishnamurthy, Prabhu ^a   Madge, Robert ^a   Keim, Martin ^b   Kassab, Mark ^b   Rajski, Janusz ^b  

^a AGERE SYSTEMS   (United States)

^b MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TESTING; COMPUTER SIMULATION; DELAY CIRCUITS; ELECTRIC FAULT CURRENTS; ELECTRIC RESISTANCE; LOGIC GATES; MATHEMATICAL MODELS; PATTERN RECOGNITION; SEMICONDUCTING SILICON;

INLINE RESISTANCE FAULT (IRF) MODEL; STUCK-AT FAULT (SAF) MODEL; TRANSITION DELAY FAULT (TDF); VERY DEEP SUB MICRON (VDSM);

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 18144391597     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. R. D. Eldred, "Test Routines Based on Symbolic Logical Statements," Journal of the ACM, Volume 6, Issue 1, pp. 33-36, 1959
2. M. A. Breuer, A. D. Friedman, "Diagnosis & Reliable Design of Digital Systems", Computer Science Presss, 1976
3. B. R. Benware, R. Madge, C. Lu, and Dr. R. Daasch "Effectiveness Comparisons of Outlier Screening Methods for Frequency Dependent Defects on Complex ASICs", VTS, pp. 39-46, 2003
4. W. Needham, C. Prunty, E. H. Yeoh, "High Volume Microprocessor Test Escapes, an Analysis of Defects our Tests are Missing", ITC, pp. 25-34, 1998
5. J. Rajski, M. Kassab, N. Mukherjee, N. Tamarapalli, J. Tyszer, J. Qian, "Embedded deterministic test for low-cost manufacturing", IEEE Design & Test of Computers, Volume 20, Issue 5, pp. 58-66, Sept.-Oct. 2003
6. P. Wohl, J. A. Waicukauski, S. Patel, M. B. Amin, "Efficient Compression and Application of Deterministic Patterns in a Logic Bist Architecture", DAC, pp. 566-569, 2003
7. F. Poehl, M. Beck, R. Arnold, P. Muhmenthaler, N. Tamarapalli, M. Kassab, N. Mukherjee, J. Rajski, "Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions", ITC, pp. 1211-1220, 2003
8. W. Moore, G. Gronthoud, K. Baker, M. Lousberg, "Delay-Fault Testing and Defect in Deep Sub-Micron ICs - Does Critical Resistance Really Mean Anything?", ITC, pp. 95-104, 2000
9. K. Baker, G. Gronthoud, M. Lousberg, I. Schanstra, C. Hawkins, "Defect-Based Delay Testing of Resistive Vias-Contacts A Critical Evaluation", ITC, pp. 467-476, 1999
10. S. Chakravarty, A. Jain, "Fault Models for Speed Failures Caused by Bridges and Opens", VTS, pp. 1-6, 2002
11. A. Krishnamachary, J. A. Abreaham, "Test Generation for Resistive Opens in CMOS", Great Lake Symposium on VLSI, pp. 65-70, 2002
12. E. J. McCluskey, A. Al-Yamani, J. C.-M Li, C. Tseng, E. Volkerink, F. Ferhani, E. Li, S. Mitra, "ELF-Murphy Data on Defects and Test Sets", VTS, pp. 16-22, 2004
13. B. Benware, C. Schuermyer, S. Ranganathan, R. Madge, P. Krishnamurthy, N. Tamarapalli, K.-H. Tsai, J. Rajski, "Impact of Multiple-Detect Test Patterns on Product Quality", ITC, pp. 103-1040, 2003
14. R. Madge, M. Rehani, K. Cota and R. Daasch, "Statistical Post-Processing at Wafersort - An alternative to Burn-in and a manufacturable solution to test limit setting for sub-micron technologies", Proc. VLSI Test Symposium, 2002