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Volumn , Issue , 2004, Pages 57-66

Logic BIST with scan chain segmentation

Author keywords

[No Author keywords available]

Indexed keywords

CELLULAR AUTOMATON (CA); CIRCUIT UNDER TEST (CUT); LINEAR FEEDBACK SHIFT REGISTERS (LFSR); PSEUDO RANDOM PATTERN GENERATOR; WEIGHTED RANDOM PATTERN TESTING (WRPT);

EID: 18144383046     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (17)

References (29)
  • 3
    • 0022893965 scopus 로고
    • Random pattern testability by fast fault simulation
    • A. J. Briers and K.A.E. Totton, "Random Pattern Testability by Fast Fault Simulation", Proc. of Int'l Test Conf., pp.214-281, 1986.
    • (1986) Proc. of Int'l Test Conf. , pp. 214-281
    • Briers, A.J.1    Totton, K.A.E.2
  • 5
    • 0028484273 scopus 로고
    • An observability enhancement approach for improved testability and at-speed test
    • E. M. Rudnick, V. Chickermane, and J. H. Patel, "An Observability Enhancement Approach for Improved Testability and At-Speed Test", IEEE Trans. on CAD, Vol.13, No.8, pp. 1051-1056, 1994.
    • (1994) IEEE Trans. on CAD , vol.13 , Issue.8 , pp. 1051-1056
    • Rudnick, E.M.1    Chickermane, V.2    Patel, J.H.3
  • 6
    • 0030404034 scopus 로고    scopus 로고
    • Constructive multi-phase test point insertion for scan-based BIST
    • N. Tamarapalli, J. Rajski, "Constructive Multi-Phase Test Point Insertion for Scan-Based BIST", Proc. of Int'l Test Conf., pp649-658, 1996.
    • (1996) Proc. of Int'l Test Conf. , pp. 649-658
    • Tamarapalli, N.1    Rajski, J.2
  • 9
    • 0024125931 scopus 로고
    • Multiple distributions for biased random test patterns
    • H. J. Wunderlich, "Multiple Distributions for Biased Random Test Patterns", Proc. of Int'l Test Conf., pp.236-244, 1988.
    • (1988) Proc. of Int'l Test Conf. , pp. 236-244
    • Wunderlich, H.J.1
  • 11
    • 0024915808 scopus 로고
    • Hardware-based weighted random pattern generation for boundary scan
    • F. Brglez, C. Gloster, and G. Kedem, "Hardware-based weighted random pattern generation for boundary scan,", Proc. of Int'l Test Conf., pp.264-273, 1989.
    • (1989) Proc. of Int'l Test Conf. , pp. 264-273
    • Brglez, F.1    Gloster, C.2    Kedem, G.3
  • 13
    • 0027629166 scopus 로고
    • 3-weight pseudo-random test generation based on deterministic test set for combinational and sequential circuits
    • I. Pomeranz and S. M. Reddy, "3-Weight Pseudo-Random Test Generation Based on Deterministic Test Set for Combinational and Sequential Circuits,", IEEE Trans. on CAD of Integrated Circuits and Systems, Vol.12, No. 7, pp. 1050-1058, 1993.
    • (1993) IEEE Trans. on CAD of Integrated Circuits and Systems , vol.12 , Issue.7 , pp. 1050-1058
    • Pomeranz, I.1    Reddy, S.M.2
  • 14
    • 18144419250 scopus 로고
    • On numerical weight optimization for random testing
    • J. Hartmann. "On Numerical Weight Optimization for Random Testing", Proc. of the joint EDAC-EUROASIC Conf, pp. 223-230, 1993.
    • (1993) Proc. of the Joint EDAC-EUROASIC Conf , pp. 223-230
    • Hartmann, J.1
  • 15
    • 0035687713 scopus 로고    scopus 로고
    • 99% AC test coverage using only LBIST on the 1 GHz IBM S390 zSeries 900 microprocessor
    • M. P. Kusko, B. J. Robbins, T. J. Koprowski, W. V. Huott, "99% AC test coverage using only LBIST on the 1 GHz IBM S390 zSeries 900 Microprocessor", Proc. of Int'l Test Conf., pp. 586-592, 2001.
    • (2001) Proc. of Int'l Test Conf. , pp. 586-592
    • Kusko, M.P.1    Robbins, B.J.2    Koprowski, T.J.3    Huott, W.V.4
  • 17
    • 0026675962 scopus 로고
    • Cube-contained random patterns and their application to the complete testing of synthesized multi-level circuits
    • S. Pateras and J. Rajski, "Cube-Contained Random Patterns and their Application to the Complete Testing of Synthesized Multi-Level Circuits", Proc. of Int'l Test Conf, pp. 473-482, 1991.
    • (1991) Proc. of Int'l Test Conf , pp. 473-482
    • Pateras, S.1    Rajski, J.2
  • 18
    • 0029252184 scopus 로고
    • Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers
    • Feb.
    • S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, and B. Courtois, "Built-in Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers", IEEE Trans. on Comp., Vol. C-44, pp. 223-233, Feb. 1995.
    • (1995) IEEE Trans. on Comp. , vol.C-44 , pp. 223-233
    • Hellebrand, S.1    Rajski, J.2    Tarnick, S.3    Venkataraman, S.4    Courtois, B.5
  • 19
    • 0002446741 scopus 로고
    • LFSR-coded test patterns for scan designs
    • B. Koenemann, "LFSR-Coded Test Patterns for Scan Designs", Proc. of Euro. Test Conf., pp.237-242, 1991.
    • (1991) Proc. of Euro. Test Conf. , pp. 237-242
    • Koenemann, B.1
  • 20
    • 0029213814 scopus 로고
    • A novel pattern generator for near perfect fault-coverage
    • M. Chatterjee, and D. K. Pradhan, "A Novel Pattern Generator for Near Perfect Fault-Coverage", Proc. of Int'l Test Conf., pp.417-425, 1995.
    • (1995) Proc. of Int'l Test Conf. , pp. 417-425
    • Chatterjee, M.1    Pradhan, D.K.2
  • 21
  • 22
    • 0030388310 scopus 로고    scopus 로고
    • Altering a pseudo-random bit sequence for scan-based BIST
    • N. A. Touba and E. J. McCluskey, "Altering A Pseudo-Random Bit Sequence for Scan-Based BIST", Proc. of Int'l Test Conf., pp. 167-175, 1996.
    • (1996) Proc. of Int'l Test Conf. , pp. 167-175
    • Touba, N.A.1    McCluskey, E.J.2
  • 25
    • 0002609165 scopus 로고
    • A neutral netlist of 10 combinational benchmark designs and a special translator in fortran
    • June
    • F. Brglez and H. Fujiwara, "A Neutral Netlist of 10 Combinational Benchmark Designs and A Special Translator in Fortran", Proc. Intl. Symp on Circuits and Systems, June 1985.
    • (1985) Proc. Intl. Symp on Circuits and Systems
    • Brglez, F.1    Fujiwara, H.2
  • 27
    • 0032306250 scopus 로고    scopus 로고
    • Automated synthesis of large phase shifters for built-in self-test
    • J. Rajski, N. Tamarapalli and J. Tyszer, "Automated Synthesis of Large Phase Shifters for Built-in Self-Test", Proc. of Int'l Test Conf., pp. 1047-1056, 1998.
    • (1998) Proc. of Int'l Test Conf. , pp. 1047-1056
    • Rajski, J.1    Tamarapalli, N.2    Tyszer, J.3
  • 28
    • 0032319387 scopus 로고    scopus 로고
    • New techniques for deterministic test pattern generation
    • I. Hamzaoglu and J. H. Patel, "New Techniques for Deterministic Test pattern Generation", Proc. of VLSI Test Symp., pp. 446-452, 1998.
    • (1998) Proc. of VLSI Test Symp. , pp. 446-452
    • Hamzaoglu, I.1    Patel, J.H.2
  • 29
    • 0002376728 scopus 로고
    • Fault simulation for structured VLSI
    • Dec.
    • J. A. Waicukauski, etc, "Fault Simulation for Structured VLSI", VLSI Systems Design, Vol. 6, No. 12, pp. 20-32, Dec. 1985.
    • (1985) VLSI Systems Design , vol.6 , Issue.12 , pp. 20-32
    • Waicukauski, J.A.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.