Conflict-free parallel memory access scheme for FFT processors

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 2003, Pages

  Takala, Jarmo H ^a   Järvinen, Tuomas S ^a   Sorokin, Harri T ^a  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATION THEORY; DATA STORAGE EQUIPMENT; FAST FOURIER TRANSFORMS; MATRIX ALGEBRA;

PARALLEL MEMORY ACCESS;

PARALLEL PROCESSING SYSTEMS;

EID: 17644444379     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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7. A. Norton and E. Melton, "A class of boolean linear transformations for conflict-free power-of-two stride access," in Proc. Int. Conf. Parallel Processing, St. Charles, IL, U.S.A., Aug. 17-21 1987, pp. 247-254.
8. D. T. Harper III, "Block, multistride vector, and FFT accesses in parallel memory systems," IEEE Trans. Parallel and Distrib. Syst., vol. 2, no. 1, pp. 43-51, Jan. 1991.
9. J. Granata, M. Conner, and R. Tolimieri, "Recursive fast algorithms and the role of the tensor product," IEEE Trans. Signal Processing, vol. 40, no. 12, pp. 2921-2930, Dec. 1992.
10. D. T. Harper III, "Increased memory performance during vector accesses through the use of linear address transformations," IEEE Trans. Comput., vol. 41, no. 2, pp. 227-230, Feb. 1992.