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Volumn 4, Issue , 1999, Pages 1921-1924

A NOVEL MEMORY-BASED FFT PROCESSOR FOR DMTIOFDM APPLICATIONS

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN FOR TESTABILITY; MEMORY ARCHITECTURE;

EID: 0037994648     PISSN: 15206149     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASSP.1999.758300     Document Type: Conference Paper
Times cited : (24)

References (14)
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    • J. S. Chow, J. C. Tu, and J. M. Cioffi, "A discrete multitone transceiver system for HDSL applications," IEEE J. Select. Areas Commun., vol. 9, pp. 895-908, Aug. 1991.
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  • 3
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    • Le Floch, B.1    Alard, M.2    Berrou, C.3
  • 4
    • 85188336889 scopus 로고
    • American National Standard - Tl.413-1995, New York, NY
    • American National Standard - Tl.413-1995, "ADSL Metallic Interface Specification," New York, NY, 1995.
    • (1995) ADSL Metallic Interface Specification
  • 7
    • 0031344760 scopus 로고    scopus 로고
    • Overview of multicarrier CDMA
    • Dec.
    • S. Hara and R. Prasad, "Overview of multicarrier CDMA," IEEE Commun. Mag., vol. 35, pp. 126-133, Dec. 1997.
    • (1997) IEEE Commun. Mag. , vol.35 , pp. 126-133
    • Hara, S.1    Prasad, R.2
  • 9
    • 0024479933 scopus 로고
    • Efficient one-dimensional systolic array realization of discrete Fourier transform
    • Jan.
    • J. A. Beraldin, T. Aboulnasr, and W. Steenaart, "Efficient one-dimensional systolic array realization of discrete Fourier transform," IEEE Trans. Circuits Syst., vol. 36, pp. 95-100, Jan. 1989.
    • (1989) IEEE Trans. Circuits Syst. , vol.36 , pp. 95-100
    • Beraldin, J.A.1    Aboulnasr, T.2    Steenaart, W.3
  • 10
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    • A new linear systolic array for FFT computation
    • Apr.
    • J. Choi, and V. Boriakoff, "A new linear systolic array for FFT computation," IEEE Trans. Circuits Syst.-II., vol. 39, pp. 236-239, Apr. 1992.
    • (1992) IEEE Trans. Circuits Syst.-II. , vol.39 , pp. 236-239
    • Choi, J.1    Boriakoff, V.2
  • 11
    • 0043263235 scopus 로고
    • FFT computation with systolic arrays, a new architecture
    • Apr.
    • V. Boriakoff, "FFT computation with systolic arrays, a new architecture," IEEE Trans. Circuits Syst.-II., vol. 41, pp. 278-284, Apr. 1994.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.