A low jitter triple-band digital LC PLL in 130nm CMOS

ESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference

Volumn , Issue , 2004, Pages 371-374

  Da Dalt, Nicola ^a   Thaller, Edwin ^a   Gregorius, Peter ^b   Gazsi, Lajos ^b  

^a INFINEON TECHNOLOGIES AUSTRIA AG   (Austria)

^b INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL CONTROL SYSTEMS; ELECTRIC COILS; JITTER; PHASE LOCKED LOOPS; PHASE MODULATION; SPURIOUS SIGNAL NOISE; SYNCHRONIZATION; VARIABLE FREQUENCY OSCILLATORS;

DIGITALLY CONTROLLED LC OSCILLATORS; LOW JITTER CLOCK; SYSTEMS ON CHIP (SOC); TRIPLE-BAND OPERATION;

DIGITAL CIRCUITS;

EID: 17644421894     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. R.B. Staszewski et al., "All-Digital Phase Domain TX Frequency Synthesizer for Bluetooth Radios in 0.13um CMOS", in Proc. of the ISSCC 2004
2. R. Walker, "Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems", in Phase-Locking in High Performance Systems, IEEE Press, 2003
3. M. Tiebout, "A CMOS Fully Integrated 1 GHz and 2 GHz Dual Band VCO with a Voltage Controlled Inductor", Proc. of the ESSCIRC, 2002
4. Y.M Greshishchev et al., "A Fully Integrated SiGe Receiver IC for 10-Gb/s Data Rate", IEEE J. Solid-State Circuits, Vol. 35, No. 12, Dec. 2000, pp. 1949-1957
5. Y. Choi et al., "Jitter Transfer Analysis of Tracked Oversampling Techniques for Multigigabit Clock and Data Recovery", IEEE Trans. Circuits Syst. II, Vol. 50, No. 11, Nov. 2003, pp.775-783
6. N. Da Dalt, "A Design Oriented Study of the Nonlinear Dynamics of Digital Bang-Bang PLLs", submitted for publication to IEEE Trans. Circuits Syst. I