Evaluating techniques for exploiting instruction slack

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2004, Pages 375-378

  Chin, Yau ^a   Sheu, John ^a   Brooks, David ^a  

^a HARVARD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK FREQUENCIES; LEAKAGE POWER; POWER DISSIPATION; POWER SAVINGS;

ALGORITHMS; BANDWIDTH; DATA STORAGE EQUIPMENT; DECODING; ELECTRIC CLOCKS; ELECTRIC POTENTIAL; ELECTRIC POWER MEASUREMENT; ENERGY EFFICIENCY; METADATA; MICROPROCESSOR CHIPS; MULTIMEDIA SYSTEMS; PERSONAL COMPUTERS; SCHEDULING; SERVERS;

PROGRAM PROCESSORS;

EID: 17644404825     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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3. B. Fields, R. Bodik, and M. D. Hill. Slack: Maximizing performance under technological constraints. In 29th International Symposium on Computer Architecture, May 2002.
4. S. Jung et al. Dual threshold voltage domino logic synthesis for high performance with delay and power constraint. In Design, Automation and Test in Europe, 2002.
5. V. Oklobdzija et al. Energy-delay estimation technique for high-performance microprocessor VLSI adders. In International Symposium on Computer Arithmetic, June 2003.
6. T. Pering, T. Burd, and R. Broderson. Voltage scheduling in the 1pARM microprocessor system. In ISLPED, July 2000.
7. R. Pyreddy and G. Tyson. Evaluating design tradeoffs in dual speed pipelines. In Work. on Complex. Eff. Design, June '01.
8. G. Semeraro et al. Dynamic frequency and voltage control for a multiple clock domain microarchitecture. In 35th International Symposium on Microarchitecture, November 2002.
9. J. Seng, E. Tune, and D. Tullsen. Reducing power with dynamic critical path information. In MICRO34, Dec. 2001.