Exploiting quiescent states in register lifetime

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2004, Pages 368-374

  Sangireddy, Rama ^a   Somani, Arun K ^b  

^a The University of Texas at Dallas   (United States)

^b Iowa State University of Science and Technology   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; CONFORMAL MAPPING; MULTIPLEXING; PROGRAM PROCESSORS; SUPERVISORY AND EXECUTIVE PROGRAMS; THROUGHPUT;

INSTRUCTIONS PER CYCLE (IPC); INSTRUCTIONS PER SECOND (IPS); RE-ORDER BUFFER (ROB); REGISTER UPDATE UNIT (RUU);

FILE ORGANIZATION;

EID: 17644383403     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

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