Using RT level component descriptions for single stuck-at hierarchical fault simulation

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 20, Issue 6, 2004, Pages 575-589

  Navabi, Zainalabedin ^a   Mirkhani, Shahrzad ^a   Lavasani, Meisam ^a   Lombardi, Fabrizio ^b  

^a UNIVERSITY OF TEHRAN   (Iran)

^b Northeastern University   (United States)

Author keywords

Delta times; Hierarchical fault simulation; Mixed level; Register transfer level; VHDL

Indexed keywords

DELTA TIMES; HIERARCHICAL FAULT SIMULATION; MIXED LEVELS; REGISTER TRANSFER LEVEL; VHDL;

AUTOMATION; COMPUTER SIMULATION; COMPUTER SOFTWARE; CONCURRENCY CONTROL; GATES (TRANSISTOR); OBJECT ORIENTED PROGRAMMING;

INTEGRATED CIRCUIT TESTING;

EID: 17044362241     PISSN: 09238174     EISSN: 15730727     Source Type: Journal    
DOI: 10.1007/s10677-004-4247-z     Document Type: Conference Paper

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