EEPROM memory stack with scaled down thickness

Microelectronic Engineering

Volumn 72, Issue 1-4, 2004, Pages 421-425

  Edelstein, Ruth Shima ^a   Cork, Chris ^a   Aloni, Efraim ^a   Vofsy, Nachi ^a   Roizin, Yakov ^a  

^a Tower Semiconductors Ltd ^*  (Israel)

Author keywords

Amorphous Si; Breakdown; EEPROM; Multi bit memory cell; Scaling

Indexed keywords

AMORPHOUS SILICON; CHEMICAL VAPOR DEPOSITION; ELECTRIC BREAKDOWN; ELECTRIC CHARGE; ELECTRON TRAPS; GATES (TRANSISTOR); GRAIN BOUNDARIES; HOLE TRAPS; HOT CARRIERS; IRRADIATION; OXIDATION; PHOTOIONIZATION; SILICON NITRIDE; ULTRAVIOLET RADIATION;

AMORPHOUS SI; EEPROM; MULTI-BIT MEMORY CELLS; SCALING;

PROM;

EID: 1642587316     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2004.01.038     Document Type: Conference Paper

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