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Volumn , Issue , 2003, Pages 248-254

Coarse-Grained DRAM Power Management

Author keywords

DRAM; Low power; Power mode transition; Scheduling

Indexed keywords

ELECTRIC ENERGY STORAGE; ELECTRIC POWER UTILIZATION; EMBEDDED SYSTEMS; REAL TIME SYSTEMS; SCHEDULING;

EID: 1642416110     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (1)

References (18)
  • 8
    • 0036475888 scopus 로고    scopus 로고
    • Trends in High-Performance, Low-Power Cache Memory Architectures
    • Feb.
    • K. Inoue, A. G. Moshnyaga, and K. Murakami, "Trends in High-Performance, Low-Power Cache Memory Architectures," IEICE Trans. on Electronics, Vol. E85-C, No. 2, pp. 304-314, Feb. 2002.
    • (2002) IEICE Trans. on Electronics , vol.E85-C , Issue.2 , pp. 304-314
    • Inoue, K.1    Moshnyaga, A.G.2    Murakami, K.3
  • 12
    • 1642307870 scopus 로고    scopus 로고
    • Rambus Inc. http://www.rambus.com/
  • 18
    • 0036543204 scopus 로고    scopus 로고
    • Power-Optimal Encoding for a DRAM Address Bus
    • April
    • W-C Cheng and M. Pedram, "Power-Optimal Encoding for a DRAM Address Bus," IEEE Trans. on VLSI Systems, Vol. 10, Issue 2, pp. 109-118, April 2002.
    • (2002) IEEE Trans. on VLSI Systems , vol.10 , Issue.2 , pp. 109-118
    • Cheng, W.-C.1    Pedram, M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.