Impact of Code Compression on the Power Consumption in Embedded Systems

Proceedings of the International Conference on Embedded Systems and Applications

Volumn , Issue , 2003, Pages 197-203

  Kadri, N ^a   Niar, S ^b   Baba Ali, A R ^a  

^a UNIVERSITY OF SCIENCES AND TECHNOLOGY HOUARI BOUMEDIENE   (Algeria)

^b LAMIH   (France)

Author keywords

Code compression; Computer architecture; Power consumption

Indexed keywords

CODES (SYMBOLS); COMPUTER ARCHITECTURE; COMPUTER SOFTWARE; ELECTRIC POWER UTILIZATION; PERSONAL DIGITAL ASSISTANTS;

CODE COMPRESSION;

EMBEDDED SYSTEMS;

EID: 1642322120     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)

1. H.Lekatsas and W.Wolf, Code Compression for Embedded systems, proceedings of the DAC'98.
2. L.Benini, A.Macii, E.Macii and M.Poncino, Selective Instruction Compression for Memory Energy Reduction in Embedded Systems, ISLPED'99
3. A.Wolf, A.Chanin. Executing Compressed Programs on An Embedded RISC Architecture, Proceedings of the Micro conf., 1992.
4. IBM, CodePack PowerPc Code Compression Utility User's Manual 3.0, IBM corp. 1998.
5. C.Lefurgy, T.Mudge, Fast Softwre-managed Code Decompression CASES 1999
6. Y.Xie, W.Wolf, H.Lekastas; A code compression architecture for VLIW processors; 34th Inter. Symposium on Microarchitecture, 2001
7. N.Mahapatra, J.Liu, K.Sundaresan; The performance advantage of applying compression to the memory systems, Workshop on memory system performance 2002.
8. H.Lekatsas, W.Wolf, SAMC: A Code Compression Algorithm for Embedded Processors, IEEE trans. On CAD, Dec. 1999.
9. C.Lefurgy Efficient Execution of Compressed Programs, PHD dissertation, Univ. of Michigan 2000
10. D.Buger, T.Austin, The SimpleScalare Tool Set,Version 2.0, University of Wisconsin-Madison, CS dep. Tech. Report #1342, 1997.
11. D.Brooks, V.Tiwari and M.Martonosi, Wattch: A Framework for Architectural-Level Power Analysis and Optimizations, 27th ISCA, 2000.
12. S. Wilton and N. Jouppi. An Enhanced Access and Cycle Time Model for On-Chip Caches. Research Report Western Research Lab, 93/5, July 1994.
13. Blue Logic SA-27E ASIC technical documentation, IBM corp., www.ibm.com/chips, 2002
14. M.Gutahus, J.Reingerberg, D.Ernst, T.Austin, T.Mudge, R.Brown; MiBench: A free, commercially representative embedded benchmark suite. IEEE Workshop on Workload Characterization 2001.
15. D.Marculescu; Profile-driven code excution for low power dissipation, ISPLED 2000.