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Volumn E86-D, Issue 9, 2003, Pages 1479-1486

HTN: A New Hierarchical Interconnection Network for Massively Parallel Computers

Author keywords

Hierarchical network; Layout area; Network performance; Peak number of vertical links

Indexed keywords

COMPUTATION THEORY; COSTS; HIERARCHICAL SYSTEMS; SILICON; TELECOMMUNICATION LINKS; TELECOMMUNICATION NETWORKS; THEOREM PROVING; TOPOLOGY; ULSI CIRCUITS;

EID: 1642263271     PISSN: 09168532     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article
Times cited : (33)

References (13)
  • 1
    • 0027841693 scopus 로고
    • dBCube, a new class of hierarchical multiprocessor networks and it's area efficient layout
    • Dec.
    • C. Chen, D.P. Agrawal, and J.R. Burke, "dBCube, a new class of hierarchical multiprocessor networks and it's area efficient layout," IEEE Trans. Parallel Distrib. Syst., vol.4, no.12, pp.1332-1343, Dec. 1993.
    • (1993) IEEE Trans. Parallel Distrib. Syst. , vol.4 , Issue.12 , pp. 1332-1343
    • Chen, C.1    Agrawal, D.P.2    Burke, J.R.3
  • 4
    • 0030395975 scopus 로고    scopus 로고
    • The emergence of stacked 3D silicon and its impact on microelectronics system integration
    • J. Carson, "The emergence of stacked 3D silicon and its impact on microelectronics system integration," IEEE Int'l. Conf. on Innovative System in Silicon, pp.1-8, 1996.
    • (1996) IEEE Int'l. Conf. on Innovative System in Silicon , pp. 1-8
    • Carson, J.1
  • 6
    • 0031219881 scopus 로고    scopus 로고
    • TESH: A new hierarchical interconnection network for massively parallel computing
    • Sept.
    • V.K. Jain, T. Ghirmai, and S. Horiguchi, "TESH: A new hierarchical interconnection network for massively parallel computing," IEICE Trans. Inf. & Syst., vol.E80-D, no.9, pp.837-846, Sept. 1997.
    • (1997) IEICE Trans. Inf. & Syst. , vol.E80-D , Issue.9 , pp. 837-846
    • Jain, V.K.1    Ghirmai, T.2    Horiguchi, S.3
  • 7
    • 0032167138 scopus 로고    scopus 로고
    • VLSI considerations for TESH: A new hierarchical interconnection network for 3-D integration
    • V.K. Jain and S. Horiguchi, "VLSI considerations for TESH: A new hierarchical interconnection network for 3-D integration," IEEE Trans. Very Large Scale Integr. Syst., vol.6, no.3, pp.346-353, 1998.
    • (1998) IEEE Trans. Very Large Scale Integr. Syst. , vol.6 , Issue.3 , pp. 346-353
    • Jain, V.K.1    Horiguchi, S.2
  • 9
    • 0025448089 scopus 로고
    • Performance analysis of k-ary n-cube interconnection networks
    • June
    • W.J. Dally, "Performance analysis of k-ary n-cube interconnection networks," IEEE Trans. Comput., vol.39, no.6, pp.775-785, June 1990.
    • (1990) IEEE Trans. Comput. , vol.39 , Issue.6 , pp. 775-785
    • Dally, W.J.1
  • 11
    • 1642384590 scopus 로고
    • Trends in interconnection network topologies: Hierarchical networks
    • Y.R. Potlapalli, "Trends in interconnection network topologies: Hierarchical networks," Int'l. Conf. on Parallel Processing Workshop, pp.24-29, 1995.
    • (1995) Int'l. Conf. on Parallel Processing Workshop , pp. 24-29
    • Potlapalli, Y.R.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.