Test configuration minimization for the logic cells of SRAM-Based FPGAS: A case study

Proceedings - European Test Workshop 1999, ETW 1999

Volumn , Issue , 1999, Pages 146-151

  Renovell, M ^a   Portal, J M ^a   Figueras, J ^b   Zorian, Y ^c  

^a LIRMM   (France)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^c LogicVision Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CELLS; CYTOLOGY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LOGIC DEVICES; STATIC RANDOM ACCESS STORAGE; TESTING;

BOOLEAN TESTING; CLASSICAL TECHNIQUES; CLASSICAL TESTS; KEYPOINTS; LOGIC CELLS; TEST CONFIGURATIONS;

COMPUTER CIRCUITS;

EID: 16244423825     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ETW.1999.804520     Document Type: Conference Paper

References (11)

1. S.D. Brown, R.J. Francis, J. Rose, S.G. Vranesic, Field- Programmable Gate Arrays, Kluwer Academic Publishers, 1992.
2. S.M. Trimberger (ed), Field-Programmable Gate Array Technology, Kluwer Academic Publishers, 1994.
3. M. Renovell, J.M. Portal, J. Figueras and Y. Zorian, Testing the Configurable Logic of RAM-based FPGA, IEEE Int. Conf. on Design, Automation and Test in Europe, Paris, France, Feb 1998, pp. 82-88.
4. M. Renovell, J.M.Portal, J. Figueras and Y. Zorian, Testing the Interconnect of RAM-Based FPGAs, IEEE Design & Test of Computer, Vol. 15, n°1, January-March 1998, pp.45-50.
5. M. Renovell, J.M. Portal, J. Figueras and Y. Zorian, SRAM-Based FPGA: Testing the LUT/RAM modules, IEEE International Test Conferenc, Washington, DC, USA, Nov 1998, pp. 1102-1111.
6. M. Renovell, J.M. Portal, J. Figueras and Y. Zorian, SRAM-Based FPGA: Testing the Interconnect/Logic Interface, IEEE Asian Test Symposium, Singapore, Nov 1998, pp. 266-271.
7. T. Inoue, H. Fujiwara, H. Michinishi, T. Yokohira and T. Okamoto, Universal Test Complexity of Field-Programmable Gate Arrays, 4th Asian Test Symposium, Bangalora, India, November 1995, pp. 259-265.
8. C. Stroud, P. Chen, S. Konala, M. Abramovici, Evaluation of FPGA Ressources for Built-In Self Test of Programmable Logic Blocks, Proc. of 4th ACM/SIGDA Int. Symposium on FPGAs, 1996, pp. 107-113.
9. W.K. Huang and F. Lombardi, An Approach for Testing Programmable/Configurable Field Programmable Gate Arrays, 14th IEEE VLSI Test Symposium, Princeton, NJ, USA, May 1996, pp. 450-455.
10. F. Lombardi, D. Ashen, X.T. Chen, W.K. Huang Diagnosing Programmable Interconnect Systems for FPGAs, FPGA'96, Monterey CA, USA, 1996, pp. 100-106.
11. Xilinx, The Programmable Logic Data Book , San Jose, USA, 1994.