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Volumn , Issue , 2004, Pages 152-157

A timing-accurate HW/SW co-simulation of an ISS with SystemC

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SIMULATION; COMPUTER SOFTWARE; SYNCHRONIZATION; SYSTEMS ANALYSIS;

EID: 16244415906     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1016720.1016759     Document Type: Conference Paper
Times cited : (32)

References (19)
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    • 16244415129 scopus 로고    scopus 로고
    • Synopsys Inc. Eaglei. Http://www.synopsys.com/products.
    • Eaglei
  • 4
    • 34548542914 scopus 로고    scopus 로고
    • Mentor Graphics Inc. Seamless CVE. Http://www.mentor.com/seamless.
    • Seamless CVE
  • 6
    • 0032010277 scopus 로고    scopus 로고
    • Automatic VHDL-C interface generation for distributed co-simulation: Application to large design examples
    • C. Valderrama, F. Nacabal, P. Paulin, and A. Jerraya. Automatic VHDL-C Interface Generation for Distributed Co-Simulation: Application to Large Design Examples. Design Automation for Embedded Systems, vol. 3(2/3):pp. 199-217, 1998.
    • (1998) Design Automation for Embedded Systems , vol.3 , Issue.2-3 , pp. 199-217
    • Valderrama, C.1    Nacabal, F.2    Paulin, P.3    Jerraya, A.4
  • 8
    • 0345382715 scopus 로고    scopus 로고
    • SystemC co-simulation and emulation of multi-processor SoC designs
    • L. Benini, D. Bertozzi, D. Bruni, N. Drago, F. Fummi, and M. Poncino, SystemC Co-simulation and Emulation of Multi-Processor SoC Designs. IEEE Computer, vol. 36(4):pp. 53-59. 2003.
    • (2003) IEEE Computer , vol.36 , Issue.4 , pp. 53-59
    • Benini, L.1    Bertozzi, D.2    Bruni, D.3    Drago, N.4    Fummi, F.5    Poncino, M.6
  • 11
    • 0033685462 scopus 로고    scopus 로고
    • Communication architecture tuners: A methodology for the design of high-performance communication architectures for system-on-chips
    • K. Lahiri, A. Raghunathan, G. Lakshminarayana, and S. Dey. Communication Architecture Tuners: a Methodology for the Design of High-Performance Communication Architectures for System-on-Chips. In Proc. of ACM/IEEE Design Automation Conference, pp. 513-518. 2000.
    • (2000) Proc. of ACM/IEEE Design Automation Conference , pp. 513-518
    • Lahiri, K.1    Raghunathan, A.2    Lakshminarayana, G.3    Dey, S.4
  • 15
    • 84893777453 scopus 로고    scopus 로고
    • Building fast and accurate SW simulation models based on hardware abstraction layer and simulation environment abstraction layer
    • S. Yoo, I. Bacivarov, A. Bouchhima, Y. Paviot, and A. Jerraya. Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer. In Proc. of IEEE Design Automation and Test in Europe, pp. 550-555. 2003.
    • (2003) Proc. of IEEE Design Automation and Test in Europe , pp. 550-555
    • Yoo, S.1    Bacivarov, I.2    Bouchhima, A.3    Paviot, Y.4    Jerraya, A.5
  • 18
    • 16244362973 scopus 로고    scopus 로고
    • eCos Home Page. Http://sources.redhat.com/ecos/.
    • ECos Home Page


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.