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IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2004, Pages 160-167

Delay noise pessimism reduction by logic correlations

(7) Glebov, A a Gavrilov, S a Soloviev, R a Zolotov, V b Becer, M R c Oh, C c Panda, R c

a Microstyle (Russian Federation)

b IBM T J WATSON RESEARCH CENTER (United States)

c FREESCALE SEMICONDUCTOR INC (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AGGRESSOR NETS; CROSS-COUPLING CAPACITANCES; LOGIC CORRELATIONS; STATIC TIMING ANALYSIS (STA);

BOOLEAN FUNCTIONS; CORRELATION METHODS; CROSSTALK; DELAY CIRCUITS; DIGITAL CIRCUITS; HEURISTIC METHODS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; SWITCHING; TRANSISTORS;

SPURIOUS SIGNAL NOISE;

EID: 16244401106 PISSN: 10923152 EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/ICCAD.2004.1382564 Document Type: Conference Paper

Times cited : (12)

References (10)

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4
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5
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- False noise analysis using logic implications
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