Device macromodel impact on data link performance assessment

IEEE Topical Meeting on Electrical Performance of Electronic Packaging

Volumn , Issue , 2004, Pages 239-242

  Stievano, I S ^a   Maio, I A ^a   Canavero, F G ^a   Siviero, C ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC POWER SYSTEM INTERCONNECTION; ERROR ANALYSIS; INTERSYMBOL INTERFERENCE; MATHEMATICAL MODELS; SIGNAL RECEIVERS; TELECOMMUNICATION LINKS; WAVEFORM ANALYSIS;

DATA LINKS; MACROMODELS; POWER SUPPLY NOISE; TRANSMISSION STRUCTURES;

DATA COMMUNICATION SYSTEMS;

EID: 15944368237     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. th Annual Austin IBM CAS Conference, Austin, TX, Feb. 19-20, 2004.
2. I. S. Stievano, I. A. Maio, F. G. Canavero, "Mπlog, Macromodels via Parametric Identification of Logic Gates," IEEE Transactions on Advanced Packaging, Vol. 27, No. 1, pp. 15-23, Feb. 2004
3. th IEEE Topical Meeting on Electrical Performance of Electronic Packaging, EPEP, Princeton, NJ, Oct. 27-29, 2003.
4. I. S. Stievano, I. A. Maio, F. G. Canavero, "Parametric Macromodels of Digital I/O Ports," IEEE Transactions on Advanced Packaging, Vol. 25, No. 2, pp. 255-264, May 2002.