Hardware and Interface Synthesis of FPGA Blocks using Parallelizing Code Transformations

Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems

Volumn 15, Issue 2, 2003, Pages 904-909

  Gupta, Sumit ^a   Luthra, Manev ^a   Dutt, Nikil ^a   Gupta, Rajesh ^b   Nicolau, Alex ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

FPGA; High level synthesis; Interface synthesis; Parallelizing transformations; Platform design; System synthesis

Indexed keywords

CODES (SYMBOLS); COMPUTER HARDWARE; MICROCONTROLLERS; MULTIMEDIA SYSTEMS; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS; PROGRAM PROCESSORS; SCHEDULING; USER INTERFACES;

HIGH LEVEL SYNTHESIS; INTERFACE SYNTHESIS; PARALLELIZING TRANSFORMATION; PLATFORM DESIGN; SYSTEM SYNTHESIS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 1542747731     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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