Simultaneous routing and buffering in SOC floorplan design

IEE Proceedings: Computers and Digital Techniques

Volumn 151, Issue 1, 2004, Pages 17-22

  Fang, J P ^a   Tong, Y S ^a   Chen, S J ^a,b  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONGESTION CONSTRAINTS; COST FUNCTIONS; MANHATTAN ROUTING (MR);

ALGORITHMS; APPROXIMATION THEORY; ESTIMATION; GRAPH THEORY; MATRIX ALGEBRA; OPTIMIZATION; PERTURBATION TECHNIQUES; PROBLEM SOLVING; ROUTERS; TOPOLOGY;

VLSI CIRCUITS;

EID: 1542581484     PISSN: 13502387     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cdt:20040072     Document Type: Conference Paper

References (9)

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2. Sham, C.W., Wong, W.C., and Young, E.F.Y.: 'Congestion estimation with buffer planning in floorplan design'. Proc. Conf. on Design and Test in Europe, Paris, France, March 2002, pp. 696-701
3. Cong, J., Kong, T., and Pan, D.Z.: 'Buffer block planning for interconnect-driven floorplanning'. Proc. Int. Conf. on Computer-Aided Design (ICCAD), San Jose, CA, November 1999, pp. 358-363
4. Sarkar, P., Sandararamanm, V., and Koh, C.-K.: 'Routability-driven repeater block planning for interconnect-centric floorplanning'. Proc. Int. Symp. on Physical Design, San Diego, CA, April 2000, pp. 186-191
5. Dragan, F.F., Kahng, A.B., Mandoiu, I.I., Muddu, S., and Zelikovsky, A.: 'Provably good global buffering using an available buffer block plan'. Proc. Int. Conf. on Computer-Aided Design (ICCAD), San Jose, CA, November 2000, pp. 104-109
6. Dragan, F.F., Kahng, A.B., Mandoiu, I.I., Muddu, S., and Zelikovsky, A.: 'Provably good global buffering by multiterminal multicommodity flow approximation'. Proc. Conf. on Asia South Pacific Design Automation (ASP DAC), Yokohama, Japan, January-February 2001, pp. 120-125
7. Alpert, C., Hu, J., Sapatnekar, S., and Villarrubia, P.: 'A practical methodology for early buffer and wire resource allocation'. Proc. Design Automation Conf. (DAC), Las Vegas, NV, June 2001, pp. 189-194
8. 'National technology roadmap for semiconductors', Semiconductor Industry Association, 1997
9. Lee, C.Y.: 'An algorithm for path connection and its application', IRE Trans. Electro. Comput., 1961, 20, pp. 346-365