Embedded Memory Analysis for Standard Cell ASIC Yield Enhancement

Conference Proceedings from the International Symposium for Testing and Failure Analysis

Volumn , Issue , 2000, Pages 69-75

  Gloor, Cary A ^a  

^a AGERE SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; C (PROGRAMMING LANGUAGE); DATA REDUCTION; DESIGN FOR TESTABILITY; DIES; EMBEDDED SYSTEMS; FAILURE ANALYSIS; GRAPHICAL USER INTERFACES; INTEGRATED CIRCUIT TESTING; LOGIC CIRCUITS; OBJECT ORIENTED PROGRAMMING; PROBABILISTIC LOGICS; SAMPLING; SEMICONDUCTOR DEVICE MODELS;

BITMAPS; EMBEDDED MEMORY ANALYSIS (EMA);

DATA STORAGE EQUIPMENT;

EID: 1542300879     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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2. A.J. van de Goor, "Testing Semiconductor Memories, Theory and Practice", John Wiley & Sons. Ltd. Chichester, U.K., pgs. 93-170 (1991)
3. A.J. van de Goor, I.B.S. Tlili, and S. Hamdioui, "Converting March Tests for Bit-Oriented Memories into Tests for Word-Oriented Memories", IEEE International Workshop on Memory Technology, Design and Testing, pgs. 46-52 (1998)
4. J.M. Morrissey, H.C. Chow, R. Devries, and C. Megivern. "An Approach to Memory Testing, Diagnostics and Analysis". International Test Conference Digest of Papers, pgs. 56-67 (1981)
5. David Flannagan, "Motif Tools: Streamlined GUI Design and Programming with the XMT Library", O'Reilly & Associates, Inc. (1994)
6. M. Faucher, "Pattern Recognition of Bit Fail Maps". International Test Conference Proceedings, pgs. 460-463 (1983)
7. L.T. Koh, K.L. Chok, H.M. Li, S.Y.M. Chooi, "Titanium Corrosion in 0.25um Metal Interconnects". IEEE International Interconnect Technology Conference, pgs. 47-49 (1999)