Improving the activation of the P+ region of low-temperature polycrystalline Si TFTs by using solid-phase crystallization

IEEE Transactions on Electron Devices

Volumn 52, Issue 3, 2005, Pages 429-432

  Ebiko, Y ^a   Suzuki, K ^a   Sasaki, N ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

Drain; Ge ion implantation; Low temperature; Parasitic resistance; Poly crystalline thin film transistor (TFT); Source

Indexed keywords

AMORPHIZATION; CMOS INTEGRATED CIRCUITS; CRYSTALLIZATION; ELECTRIC RESISTANCE; GERMANIUM; ION IMPLANTATION; LIQUID CRYSTAL DISPLAYS; LOW TEMPERATURE EFFECTS; POLYSILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SUBSTRATES; TRANSMISSION ELECTRON MICROSCOPY;

GERMANIUM ION IMPLANTATION; PARASITIC RESISTANCE; POLYCRYSTALLINE THIN FILM TRANSISTORS; SOURCE/DRAIN REGIONS;

THIN FILM TRANSISTORS;

EID: 15044357857     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.843870     Document Type: Article

References (14)

1. R. H. Dennard et al., "Design of ion-implanted MOSFETs with very small physical dimensions," IEEE J. Solid-State Circuits, vol. SC-9, no. 5, pp. 256-268, Oct. 1974.
2. J. R. Brews, W. Fichtner, E. H. Nicollian, and S. M. Sze, "Generalized guide for MOSFET miniaturization," IEEE Electron Device Lett., vol. EDL-1, no. 1, pp. 2-4, Jan. 1980.
3. P. Chattergee, W. R. Hunter, T. C. Holloway, and Y. T. Lin, "The impact of scaling laws on the choice of n-channel for MOS VLSI," IEEE Electron Device Lett., vol. EDL-1, pp. 220-223, 1980.
4. G. Baccarani, M. R. Wordeman, and R. H. Dennard, "Generalized scaling theory and its application to 1/4 micrometer MOSFET design," IEEE Trans. Electron Devices, vol. ED-31, pp. 452-462, 1984.
5. A. Yoshinouchi, A. Oda, Y. Murata, T. Morita, and S. Tsuchimoto, "Formation of source/drain using self-activation technique on polysilicon thin film transistors," Jpn. J. Appl. Phys., vol. 33, pp. 4833-4836, 1994.
6. V. Subramanian and K. C. Saraswat, "High-performance germaniumseeded laterally crystallized TFTs for vertical device integration," IEEE Trans. Electron Devices, vol. 45, no. 9, pp. 1934-1939, Sep. 1998.
7. D. Z. Peng, T.-C. Chang, P.-S. Shih, H.-W. Zan, T.-Y. Huang, C.-Y. Chang, and P.-T. Liu, "Polycrystalline silicon thin-film transistor with self align SiGe raised source/drain," Appl. Phys. Lett., vol. 81, no. 25, pp. 4763-4765, 2002.
8. C. D. Lindfors and K. S. Jones, "Boron solubility limits following low temperature solid phase epitaxial regrowth," in Proc. Mater. Res. Soc. Symp., vol. 669, 2001.
9. E. Landhi, S. Guimaraes, and S. Solmi, "Influence of nucleation on kinetics of boron precipitation," Appl. Phys. A, vol. 44, pp. 135-141, 1987.
10. M. C. Ozturk, J. J. Wortman, C. M. Osburn, A. Ajmera, G. A. Rozgonyi, E. Frey, W. Chu, and C. Lee, "Optimization of the germanium preamorphization condition for shallow junction," IEEE Trans. Electron Devices, vol. 35, no. 5, pp. 659-668, May 1988.
11. K. Suzuki, H. Tashiro, K. Narita, and Y. Kataoka, "High activity of B during solid phase crystallization in a pre-amorphized layer formed by Ge-ion implantation and deactivation during a subsequent thermal process," IEEE Trans. Electron Devices, vol. 51, no. 6, pp. 663-668, Jun. 2004.
12. A. Hara, F. Takeuchi, M. Takei, K. Suga, K. Yoshino, M. Chida, Y. Sano, and N. Sasaki, "Large grain poly-Si TFTs by scanning CW laser crystallization," in AM-LCD 2002 Tech. Dig., 2002, pp. 227-230.
13. J. G. J. Chern, P. Chang, R. F. Motta, and N. Godinho, "A new method to determine MOSFET channel length," IEEE Trans. Electron Devices, vol. EDL-1. no. 9, pp. 170-173, Sep. 1980.
14. H.-W. Zan, T.-C. Chang, P.-S. Shih, D.-Z. Peng, P.-Y. Kuo, T.-Y. Huang, and C.-Y. Chang, "A study of parasitic resistance effects in thin-channel polycrystalline silicon TFTs with tungsten-clad source/ drain," IEEE Electron Device Lett., vol. 24. no. 8, pp. 509-511, Aug. 2003.