Prelayout estimation of individual wire lengths

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 9, Issue 6, 2001, Pages 943-958

  Bodapati, Srinivas ^b   Najm, Farid N ^a,c  

^a IEEE   (Canada)

^b University of Illinois at Urbana Champaign   (United States)

^c UNIVERSITY OF TORONTO   (Canada)

Author keywords

Interconnect estimation; Prelayout estimation; Wire length

Indexed keywords

INTERCONNECT ESTIMATION;

ALGORITHMS; ERROR ANALYSIS; LOGIC DESIGN;

VLSI CIRCUITS;

EID: 0035704568     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.974908     Document Type: Article

References (8)

1. Using partitioning to help convergence in the standard-cell design automation methodology
2. The radical changes wrought by deep submicron IC technology
3. Standard cell interconnect length prediction from structural circuit attributes
4. A wire length estimation technique utilizing neighborhood density equations
5. Interconnection length estimation for optimized standard cell layouts
6. On wirelength estimations for row-based placement
7. Pre-layout estimation of individual wire lengths