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ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 4, Issue , 2001, Pages 174-177

Strategies for on-chip sub-nanosecond signal capture and timing measurements

(3) Abaskharoun, Naznzy a Hafed, Mohamed a Roberts, Gordon W a

a MCGILL UNIVERSITY (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CUMULATIVE DISTRIBUTION FUNCTION; DELAY-LOCKED LOOPS; MIXED-SIGNAL TEST; ON-CHIP SIGNALS; TIME AND FREQUENCY DOMAINS; TIME TO DIGITAL CONVERTERS; TIMING MEASUREMENT; VERNIER DELAY LINE;

CMOS INTEGRATED CIRCUITS;

JITTER;

EID: 0242677041 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/ISCAS.2001.922200 Document Type: Conference Paper

Times cited : (11)

References (8)

1
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- M. Hafed. G.W. Roberts, "A Stand-Alone Integrated Excitation/Extraction System for Analog BIST Applications," Proc. IEEE Custom Integrated Circuits Conference, pp. 83-86, 2000.
- (2000) Proc. IEEE Custom Integrated Circuits Conference , pp. 83-86
- Hafed, M.¹ Roberts, G.W.²

2
- 0032307265
- High speed and area efficient on-chip analog waveform extractor
- A. Hajjar, G.W. Roberts, "High Speed and Area Efficient On-Chip Analog Waveform Extractor, " Proc. IEEE International Test Conference, pp. 688-697 1998.
- (1998) Proc. IEEE International Test Conference , pp. 688-697
- Hajjar, A.¹ Roberts, G.W.²

3
- 0032307605
- Measuring jitter of high speed data channels using undersampling techniques
- W. Dalai, D. Rosenthal, "Measuring Jitter of High Speed Data Channels Using Undersampling Techniques," Proc. IEEE International Test Conference, pp. 814-818, 1998.
- (1998) Proc. IEEE International Test Conference , pp. 814-818
- Dalai, W.¹ Rosenthal, D.²

4
- 0031276490
- A semidigital dual delay-locked loop
- S. Sidiropoulos, M.A. Horowitz, "A Semidigital Dual Delay-Locked Loop," IEEE Journal of Solid-State Circuits, pp. 16831692, 1997.
- (1997) IEEE Journal of Solid-State Circuits , pp. 1683-1692
- Sidiropoulos, S.¹ Horowitz, M.A.²

5
- 0031256976
- A cmos high-speed data recovery circuit using the matched delay sampling technique
- K. Jin-Ku, L. Wentai, R.K. Cavin HI, "A CMOS High-Speed Data Recovery Circuit using the Matched Delay Sampling Technique," IEEE Journal of Solid-State Circuits, pp. 1588-1596, 1997.
- (1997) IEEE Journal of Solid-State Circuits , pp. 1588-1596
- Jin-Ku, K.¹ Wentai, L.² Cavin, H.I.R.K.³

6
- 0030409796
- Testing and characterizing jitter in 100base-tx and 155.2 mbits/s atm devices with a 1 gsample/s awg in an ate system
- B. Kulp, "Testing and Characterizing Jitter in 100Base-TX and 155.2 Mbits/s ATM Devices with a 1 GSample/s AWG in an ATE System," Proc. IEEE International Test Conference, pp. 104-111, 1996.
- (1996) Proc. IEEE International Test Conference , pp. 104-111
- Kulp, B.¹

7
- 17144435893
- A high-resolution cmos time-to-digital converter utilizing a vernier delay line
- P. Dudek, S. Szczepariski, J. Hatfield, "A High-Resolution CMOS Time-to-Digital Converter Utilizing a Vernier Delay Line," IEEE Transactions on Solid-State Circuits, pp. 240-247, 2000.
- (2000) IEEE Transactions on Solid-State Circuits , pp. 240-247
- Dudek, P.¹ Szczepariski, S.² Hatfield, J.³

8
- 0027851095
- Precise delay generation using coupled oscillators
- J. G. Maneatis, M. A. Horowitz, "Precise Delay Generation Using Coupled Oscillators," IEEE Journal of Solid-State Circuits, pp. 1273-1282, 1993.
- (1993) IEEE Journal of Solid-State Circuits , pp. 1273-1282
- Maneatis, J.G.¹ Horowitz, M.A.²

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.