Secondary radix recodings for higher radix multipliers

IEEE Transactions on Computers

Volumn 54, Issue 2, 2005, Pages 111-123

  Seidel, Peter Michael ^a   McFearin, Lee D ^a   Matula, David W ^a  

^a Southern Methodist University   (United States)

Author keywords

Binary multiplication; Booth recoding; Digit set; High radix; Mixed radix representation; Partial product reduction; Recoding

Indexed keywords

COMPUTER ARCHITECTURE; MICROPROCESSOR CHIPS; POLYNOMIALS; THEOREM PROVING; VECTORS;

BINARY MULTIPLICATION; BOOTH RECODING; DIGIT SET; HIGH RADIX MULTIPLIERS; MIXED RADIX REPRESENTATION; PARTIAL PRODUCT REDUCTION; RECODING;

MULTIPLYING CIRCUITS;

EID: 14844366757     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2005.32     Document Type: Article

References (14)

1. H. Al-Twaijry, "Area and Performance Optimized CMOS Multipliers," PhD thesis, Stanford Univ., Aug. 1997.
2. G.W. Bewick, "Fast Multiplication: Algorithms and Implementation," PhD thesis, Stanford Univ., Mar. 1994.
3. A.D. Booth, "A Signed Binary Multiplication Technique," Quarterly J. Mechanical and Applied Math., vol. 4, no. 2, pp. 236-240, 1951.
4. B.S. Cherkauer and E.G. Friedman, "A Hybrid Radix-4/Radix-8 Low Power Signed Multiplier Architecture," IEEE Trans. Computers, vol. 44, no. 8, pp. 656-659, Aug. 1995.
5. J. Clouser, M. Matson, R. Badeau, R. Dupcak, S. Samudrala, R. Allmon, and N. Fairbanks, "A 600-MHz Superscalar Floating-Point Processor," IEEE J. Solid-State Circuits, vol. 34, no. 7, pp. 1026-1029, 1999.
6. M. Ercegovac and T. Lang, Digital Arithmetic. Morgan Kaufmann, 2004.
7. IEEE Standard for Binary Floating-Point Arithmetic, ANSI/IEEE754-1985, New York, 1985
8. C.N. Lyu and D.W. Matula, "Redundant Binary Booth Recoding," Proc. 12th IEEE Int'l Symp. Computer Arithmetic (Arith12), pp. 50-57, 1995.
9. P.E. Madrid, B. Millar, and E.E. Swartzlander, "Modified Booth Algorithm for High Radix Multiplication," Proc. IEEE Computer Design Conf., pp. 118-121, 1992.
10. D.W. Matula, "Basic Digit Sets for Radix Representations," J. ACM vol. 29, no. 4, pp. 1131-1143, 1982.
11. S.M. Mueller and W.J. Paul, Computer Architecture - Complexity and Correctness. Springer, 2000.
12. W.J. Paul and P.-M Seidel, "To Booth or Not to Booth?" INTEGRATION, the VLSI J., vol. 32, pp. 5-40, 2002.
13. L.P. Rubinfeld, "A Proof of the Modified Booth's Algorithm for Multiplication," IEEE Trans. Computers, vol. 24, no. 10, pp. 1014-1015 Oct. 1975.
14. P.-M. Seidel, L. McFearin, and D.W. Matula, "Binary Multiplication Radix-32 and Radix-256," Proc. 15th IEEE Int'l Symp. Computer Arithmetic (Arith15), pp. 23-32, 2001.