Binary multiplication radix-32 and radix-256

Proceedings - Symposium on Computer Arithmetic

Volumn , Issue , 2001, Pages 23-32

  Seidel, P M ^a   McFearin, L D ^a   Matula, D W ^a  

^a Southern Methodist University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY SEQUENCES; COMPUTATIONAL METHODS; MULTIPLYING CIRCUITS;

BINARY MULTIPLICATION; MULTIPLICATION RADIX;

DIGITAL ARITHMETIC;

EID: 0034864096     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

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2. A 600-MHz superscalar floating-point processor
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4. Basic digit sets for radix representations
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6. On the complexity of booth recoding
7. A proof of the modified Booth's algorithm for multiplication
8. A radix-8 CMOS S/390 multiplier
9. A suggestion for parallel multipliers
10. High-speed booth encoded parallel multiplier design
11. 167 MHz radix-4 floating point multiplier