600-MHz superscalar floating-point processor

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 7, 1999, Pages 1026-1029

  Clouser, J ^a   Matson, M ^a   Badeau, R ^a   Dupcak, R ^a   Samudrala, S ^a   Allmon, R ^a   Fairbanks, N ^a  

^a HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL ARITHMETIC; ELECTRIC POWER SUPPLIES TO APPARATUS; PERFORMANCE; PIPELINE PROCESSING SYSTEMS; REDUCED INSTRUCTION SET COMPUTING; TIMING CIRCUITS;

FLOATING POINT PROCESSOR; LATCHLESS PIPELINING; OUT OF ORDER EXECUTION; SINGLE NODE GLOBAL CLOCK;

MICROPROCESSOR CHIPS;

EID: 0033366136     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.772419     Document Type: Article

References (4)

1. B. Gieseke, R. Allmon, D. Bailey, B. Benschneider, S. Britton, J. Clouser, H. Fair III, J. Farrell, M. Gowan, C. Houghton, J. Keller, T. Lee, D. Leibholz, S. Lowell, M. Matson, R. Matthew, V. Peng, M. Quinn, D. Priore, M. Smith, and K. Wilcox, "A 600 MHz superscalar RISC microprocessor with out-of-order execution," in ISSCC Dig. Tech. Papers, Feb. 1997, pp. 176-177.
2. J. Kowaleski, Jr., G. Wolrich, T. Fischer, R. Dupcak, P. Kroesen, T. Pham, and A. Olesin, "A dual-execution pipelined floating-point CMOS processor," in ISSCC Dig. Tech. Papers, Feb. 1996, pp. 358-359.
3. E. Shriver, D. Hall, N. Nassif, N. Rahman, N. Rethman, G. Watt, and J. Farrell, "Timing verification of the 21 264: A 600 MHz full-custom microprocessor," in Proc. 1998 IEEE Int. Conf. Computer Design, Oct. 1998, pp. 96-103.
4. D. Bailey and B. Benschneider, "Clocking design and analysis for a 600-MHz Alpha microprocessor," IEEE J. Solid-Suite Circuits, vol. 33, pp. 1627-1633, Nov. 1998.