Analysis and design of monolithic, high PSR, linear regulators for SoC applications

Proceedings - IEEE International SOC Conference

Volumn , Issue , 2004, Pages 311-315

  Gupta, Vishal ^a   Rincón Mora, Gabriel A ^a   Raha, Prasun ^b  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LINEAR REGULATORS; NMOS DEVICES; POWER SUPPLY REJECTION (PSR); UNITY-GAIN FREQUENCY (UGF);

BANDWIDTH; CAPACITANCE; CAPACITORS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC NETWORK TOPOLOGY; ELECTRIC POTENTIAL; ELECTRIC POWER SYSTEMS; ELECTRIC RESISTANCE; MATHEMATICAL MODELS; MOS DEVICES; NATURAL FREQUENCIES; POWER AMPLIFIERS; VOLTAGE DIVIDERS;

ELECTRIC CURRENT REGULATORS;

EID: 14844293477     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. M. S. J, Steyaert, W. M. C. Sansen, "Power supply rejection ratio in operational transconductance amplifiers," IEEE Trans. Circuits Sys., vol. 37, pp. 1077-1084, Sept 1990.
2. E. Sackinger, J. Goette, W. Guggenbül, "A general relationship between amplifier parameters, and its application to PSRR improvement," IEEE Trans. Circuits Sys., vol. 38, pp. 1173-1181, Oct. 1991.
3. H. Tanaka, M. Aoki, T. Sakata, S.Kimura, N. Sakashita, H. Hidaka, T. Tachibana, and K. Kimura, "A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme," IEEE Jour. of Solid-State Circuits, vol. 34, pp. 1084-1090, Aug. 1999.
4. V.R. von Kaenel, "A high-speed, low-power clock generator for a microprocessor application," IEEE Jour. of Solid-State Circuits, vol. 33, pp.1634-1639, Nov. 1998.
5. C.Lee, K. McClellan, and J. Choma Jr., "A supply-noise-insensitive CMOS PLL with a voltage regulator using dc-dc capacitive converter," IEEE Jour. of Solid-State Circuits, vol. 36, pp. 1453-1463, Oct. 2001.
6. J. Shor, Y. Sofer, Y. Polansky, and E. Maayan, "Low power voltage regulator for EPROM applications," in Proc. IEEE Intl. Symp. Circuits and Sys., 2002, pp. 56-579.
7. G.W. den Besten and B. Nauta, "Embedded 5V-to-3.3V voltage regulator for supplying digital IC's in 3.3V CMOS technology," IEEE Jour, of Solid-State Circuits, vol. 33, pp. 956-962, July 1998.
8. V. Balan, "A low-voltage regulator circuit with self-bias to improve accuracy," IEEE Jour. Solid State Circuits, vol. 38, pp. 365-368, Feb. 2003.
9. rd IEEE PESC, 2002, pp. 421-424.
10. H. Shin, S. Reynolds, K. Wrenner, T. Rajeevakumar, and S. Gowda, "Low-dropout on-chip voltage regulator for low-power circuits," in IEEE Symp. Low Power Electronics, 1994, pp. 76-77.
11. P.E. Allen and D.R. Holberg, CMOS Analog Circuit Design. New York, NY: Oxford University Press, 2002.