A 2-nW 1.1 -V Self-Biased Current Reference in CMOS Technology

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 52, Issue 2, 2005, Pages 61-65

  Camacho Galeano, Edgar Mauricio ^a   Galup Montoro, Carlos ^a   Schneider, Marcio Cherem ^a  

^a FEDERAL UNIVERSITY OF SANTA CATARINA   (Brazil)

Author keywords

CMOS analog integrated circuit; current source; low voltage; proportional to absolute temperature (PTAT) voltage

Indexed keywords

COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC NETWORK TOPOLOGY; ELECTRIC POTENTIAL; MATHEMATICAL MODELS; MOSFET DEVICES; TEMPERATURE;

CMOS ANALOG INTEGRATED CIRCUIT; PROPORTIONAL-TO-ABSOLUTE TEMPERATURE (PTAT) VOLTAGE; SELF BIASED CURRENT SOURCE;

CMOS INTEGRATED CIRCUITS;

EID: 14644436467     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2004.842059     Document Type: Article

References (12)

1. S. Tang, S. Narendra, and V. De, “Temperature and process invariant MOS-based reference current generation circuits for sub-1 V operation,” in Proc. ISLPED '03, pp. 199–204.
2. W. M. Sansen, F. O. Eynde, and M. Steyaert, “A CMOS temperature-compensated current reference,” IEEE J. Solid-State Circuits, vol. 23, pp. 821–824, Jun. 1988.
3. C.-H. Lee and H.-J. Park, “All-CMOS temperature independent current reference,” Electron. Lett., vol. 32, no. 14, pp. 1280–1281, 1996.
4. S. Yan and E. Sanchez-Sinencio, “Low voltage analog circuit design techniques: A tutorial,” IEICE Trans. Fund., vol. E83-A, no. 2, pp. 1–17, Feb. 2000.
5. B. Linares-Barranco and T. Serrano-Gotarredona, “On the design and characterization of femtoampere current-mode circuits,” IEEE J. Solid-State Circuits, vol. 38, no. 8, pp. 1353–1363, Aug. 2003.
6. E. Vittoz and J. Fellrath, “CMOS analog circuits based on weak inversion operation,” IEEE J. Solid-State Circuits, vol. SC-12, no. 6, pp. 224–231, Jun. 1977.
7. E. A. Vittoz and C. C. Enz, “CMOS low-power analog circuit design,” in Proc. Int. Symp. Circuits Syst. (ISCAS'96), 1996, pp. 79–133.
8. H. J. Oguey and D. Aebischer, “CMOS current reference without resistance,” IEEE J. Solid-State Circuits, vol. SC-32, no. 7, pp. 1132–1135, Jul. 1997.
9. F. Serra-Graells and J. L. Huertas, “Sub-l-V CMOS proportional-to-absolute temperature references,” IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 84–88, Jan. 2003.
10. A. I. A. Cunha, M. C. Schneider, and C. Galup-Montoro, “An MOS transistor model for analog circuit design,” IEEE J. Solid-State Circuits, vol. 33, no. 10, pp. 1510–1519, Oct. 1998.
11. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching properties of MOS transistors,” IEEEJ. Solid-State Circuits, vol. 24, no. 10, pp. 1433–1440, Oct. 1989.
12. C. Galup-Montoro, M. C. Schneider, and I. J. B. Loss, “Series-parallel association of FETs for high gain and high frequency applications,” IEEE J. Solid-State Circuits, vol. 29, no. 9, pp. 1094–1101, Sep. 1994.