A novel start-controlled phase/frequency detector for multiphase-output delay-locked loops

Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits

Volumn , Issue , 2004, Pages 68-71

  Huang, Po Jen ^a   Chen, Hou Ming ^a   Chang, Robert C ^a  

^a NATIONAL CHUNG HSING UNIVERSITY   (Taiwan)

Author keywords

Delay locked loop; Locking problem; Multiphase output; Resetable D flip flop; Start controlled circuit

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC NETWORK ANALYSIS; ENERGY UTILIZATION; FREQUENCIES; HARMONIC ANALYSIS; SIGNAL PROCESSING;

DELAY-LOCKED LOOPS; LOCKING PROBLEM; MULTIPHASE-OUTPUT; RESETBLE D-FLIP-FLOP; START-CONTROLLED CIRCUIT;

PHASE LOCKED LOOPS;

EID: 14544303694     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)

1. F. M. Gardner, "Charge-pump phase-lock loops," IEEE Trans. Commun., vol. COM-28, pp. 1849-1858, Nov. 1980.
2. B. Razavi, "Phase-locking in high-performance systems: from devices to architectures," John Wiley & Sons, Inc. 2003.
3. R. B. Watson Jr. and R. B. Iknaian, "Clock buffer chip with multiple target automatic skew compensation," IEEE J. Solid-State Circuits, vol. 30, pp. 1267-1276, Nov. 1995.
4. C. H. Kim et al., "A 64-Mbit 640-Mbyte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-Mbyte memory system," IEEE J. Solid-State Circuits, vol. 33, pp. 1703-1710, Nov. 1998.
5. Y. Moon et al., "An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance," IEEE J. Solid-State Circuits, vol. 35, pp. 377-384, Mar. 2000.
6. H. H. Chang et al., "A wide-range delay-locked loop with a fixed latency of one clock cycle," IEEE J. Solid-State Circuits, vol. 37, pp. 1021-1027, Aug. 2002.
7. S. Sidiropoulos, "High-performance inter-chip signalling," Ph.D. Dissertation, Stanford University, 1998.
8. M. J. E. Lee, "An efficient I/O and clock recovery design for terabit integrated circuits," Ph.D. dissertation, Stanford University, 2002.
9. D. J. Foley and M. P. Flynn, "CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator," IEEE J. Solid-State Circuits, vol. 36, pp. 417-423, Mar. 2001.
10. C. Kim, I. C. Hwang, and S. M. Kang, "Low-power small-area ±7.28ps jitter IGHz DLL-based clock generator," IEEE J. Solid-State Circuits, vol. 37, pp. 1414-1420, Nov. 2002.
11. H. Yahata et al., "A 256-Mb double-data-rate SDRAM with a 10-mW analog DLL circuit," Symp. VLSI Circuits Dig. Tech. Papers, pp. 74-75, June 2000.
12. S. Kim, K. Lee, Y. Moon, D. K. Jeong, Y. Choi and H. K. Kim, "A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL," IEEE J. Solid-State Circuits, vol. 32, pp. 691-700, May 1997.
13. J. Yuan and C. Svensson, "High-speed CMOS circuit technique," IEEE J. Solid-State Circuits, vol. 24, pp. 62-70, Feb. 1989.
14. D. Mijuskovic, M. Bayer, T. Chomiez. N. Garg, F. James, P. McEntarfer and J. Porter, "Cell-based fully integrated CMOS frequency synthesizers," IEEE J. Solid-State Circuits, vol. 29, pp. 271-279, Feb. 1994.
15. C. Y. Yang, "Design of clock synchronizers and frequency synthesizers," Ph.D. dissertation, National Taiwan University, 2000.
16. I. M. Filanovsky and H. Baltes, "CMOS Schmitt trigger design," IEEE Trans. On Circuits and System I, vol. 41, no 1, pp. 46-49, Jan. 1994.
17. C. Y. Yang and S. I. Liu, "A one-wire approach for skew-compensating clock distribution based on bidirectional techniques," IEEE J. Solid-State Circuits, vol. 36, pp. 266-272, Feb. 2001.